| author | Urja (ARMLFS builder)
<urja+armlfs@urja.dev> 2025-02-10 10:15:02 UTC |
| committer | Urja (ARMLFS builder)
<urja+armlfs@urja.dev> 2025-02-10 10:15:02 UTC |
| parent | c6a3950a72b5a8257fcc70792b08ce43fe7307a4 |
| .SRCINFO | +36 | -0 |
| PKGBUILD | +3 | -3 |
| armlfs.patch | +58 | -58 |
diff --git a/.SRCINFO b/.SRCINFO new file mode 100644 index 0000000..c58b842 --- /dev/null +++ b/.SRCINFO @@ -0,0 +1,36 @@ +pkgbase = linux-armlfs-lts + pkgver = 6.6.76 + pkgrel = 1 + url = http://www.kernel.org/ + arch = armv7h + license = GPL2 + makedepends = xmlto + makedepends = docbook-xsl + makedepends = kmod + makedepends = inetutils + makedepends = bc + makedepends = git + makedepends = dtc + makedepends = vboot-utils + makedepends = uboot-tools + options = !strip + source = https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.6.tar.xz + source = https://www.kernel.org/pub/linux/kernel/v6.x/patch-6.6.76.xz + source = armlfs.patch + source = kernel.its + source = kernel.keyblock + source = kernel_data_key.vbprivk + source = 60-linux.hook + source = config + sha256sums = d926a06c63dd8ac7df3f86ee1ffc2ce2a3b81a2d168484e76b5b389aba8e56d0 + sha256sums = 1fded0df787ba5ad9847ececc180399883f51e7eacb61a5c6b4edffce2067548 + sha256sums = 04efab21a4ab1a31cd027efe67c59e478e8fe5e040f7d80c8c2133add5248c13 + sha256sums = 91c73d902368f464c64626128932220a5ca7d26f7ac25eec00c1865810c51173 + sha256sums = 4e708c9ec43ac4a5d718474c9431ba6b6da3e64a9dda6afd2853a9e9e3079ffb + sha256sums = bc9e707a86e55a93f423e7bcdae4a25fd470b868e53829b91bbe2ccfbc6da27b + sha256sums = ae2e95db94ef7176207c690224169594d49445e04249d2499e9d2fbc117a0b21 + sha256sums = 0f887b4634acdb87fab95d4fa8d7574633c5f0f0e6f7da4e3f4fe34cddb915c2 + +pkgname = linux-armlfs-lts + +pkgname = linux-armlfs-lts-chromebook diff --git a/PKGBUILD b/PKGBUILD index 91596b1..f612f06 100644 --- a/PKGBUILD +++ b/PKGBUILD @@ -14,7 +14,7 @@ pkgbase=linux-armlfs${_xname} _srcname=linux-6.6 _kernelname=${pkgbase#linux} _desc="Veyron Speedy" -pkgver=6.6.43 +pkgver=6.6.76 pkgrel=1 arch=('armv7h') url="http://www.kernel.org/" @@ -169,8 +169,8 @@ for _p in ${pkgname[@]}; do done sha256sums=('d926a06c63dd8ac7df3f86ee1ffc2ce2a3b81a2d168484e76b5b389aba8e56d0' - '0407cc09f1109a1818a21e5656055822579ba4c04d18abe20e9a3cb51e62713b' - '53d3ad4009393e5df348b8ad13680dce821c3e49608c2350d5cfbca1e562ab1d' + '1fded0df787ba5ad9847ececc180399883f51e7eacb61a5c6b4edffce2067548' + '04efab21a4ab1a31cd027efe67c59e478e8fe5e040f7d80c8c2133add5248c13' '91c73d902368f464c64626128932220a5ca7d26f7ac25eec00c1865810c51173' '4e708c9ec43ac4a5d718474c9431ba6b6da3e64a9dda6afd2853a9e9e3079ffb' 'bc9e707a86e55a93f423e7bcdae4a25fd470b868e53829b91bbe2ccfbc6da27b' diff --git a/armlfs.patch b/armlfs.patch index 0ed7c1f..bfd3be7 100644 --- a/armlfs.patch +++ b/armlfs.patch @@ -1,4 +1,4 @@ -From bfdeba7d256d1fad86f596784d92499cf5a709f6 Mon Sep 17 00:00:00 2001 +From ed2488c79b73725b83f26dfad9e50e625553246e Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 10:30:55 +0000 Subject: [PATCH 01/35] drivers: clk-rk3288: support for dedicating NPLL to a @@ -166,7 +166,7 @@ index 758ebaf2236b..7ee324e4186f 100644 2.44.0 -From 7cffea41661fb1198a921d6aad050afb393f6523 Mon Sep 17 00:00:00 2001 +From 016776b5a3e979df3fe96dab2d8fa4450862ad06 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Wed, 22 Aug 2018 18:36:40 +0000 Subject: [PATCH 02/35] drm: dw_hdmi-rockchip: better clock selection logic and @@ -199,10 +199,10 @@ Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com> 1 file changed, 166 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 341550199111..4dd10e1324a4 100644 +index aae48e906af1..81f8a82aa5d4 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -81,8 +81,13 @@ struct rockchip_hdmi { +@@ -80,8 +80,13 @@ struct rockchip_hdmi { struct regulator *avdd_0v9; struct regulator *avdd_1v8; struct phy *phy; @@ -216,7 +216,7 @@ index 341550199111..4dd10e1324a4 100644 static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -@@ -90,126 +95,132 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) +@@ -89,126 +94,132 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) return container_of(rkencoder, struct rockchip_hdmi, encoder); } @@ -434,7 +434,7 @@ index 341550199111..4dd10e1324a4 100644 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); if (IS_ERR(hdmi->regmap)) { -@@ -246,39 +257,51 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) +@@ -245,39 +256,51 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) if (IS_ERR(hdmi->avdd_1v8)) return PTR_ERR(hdmi->avdd_1v8); @@ -508,7 +508,7 @@ index 341550199111..4dd10e1324a4 100644 return MODE_OK; } -@@ -294,7 +317,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, +@@ -293,7 +316,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { @@ -549,7 +549,7 @@ index 341550199111..4dd10e1324a4 100644 } static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, -@@ -350,6 +405,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, +@@ -349,6 +404,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { @@ -557,7 +557,7 @@ index 341550199111..4dd10e1324a4 100644 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, .mode_set = dw_hdmi_rockchip_encoder_mode_set, .enable = dw_hdmi_rockchip_encoder_enable, -@@ -450,7 +506,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { +@@ -451,7 +507,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { }; static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { @@ -565,7 +565,7 @@ index 341550199111..4dd10e1324a4 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -467,7 +522,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { +@@ -468,7 +523,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { }; static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { @@ -573,7 +573,7 @@ index 341550199111..4dd10e1324a4 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -487,7 +541,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { +@@ -488,7 +542,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { }; static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { @@ -581,7 +581,7 @@ index 341550199111..4dd10e1324a4 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -505,7 +558,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { +@@ -506,7 +559,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { }; static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { @@ -589,7 +589,7 @@ index 341550199111..4dd10e1324a4 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -518,7 +570,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = { +@@ -519,7 +571,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = { }; static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { @@ -597,7 +597,7 @@ index 341550199111..4dd10e1324a4 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -651,6 +702,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -652,6 +703,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return 0; err_bind: @@ -605,7 +605,7 @@ index 341550199111..4dd10e1324a4 100644 drm_encoder_cleanup(encoder); clk_disable_unprepare(hdmi->ref_clk); err_clk: -@@ -666,6 +718,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, +@@ -667,6 +719,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); @@ -617,7 +617,7 @@ index 341550199111..4dd10e1324a4 100644 2.44.0 -From cc8a191cef736ab3c1ab905927afe4d2648bb4ab Mon Sep 17 00:00:00 2001 +From 5f66439c73c3bccc07a842d80ead66782b02c79a Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 19:00:50 +0000 Subject: [PATCH 03/35] dts: rk3288: support for dedicating npll to a vop @@ -656,7 +656,7 @@ index 8593a8359937..1cfa4eda5abf 100644 2.44.0 -From e2ed63d2b240b64efcff9ba9cd119ca890647060 Mon Sep 17 00:00:00 2001 +From 61279deca53c3fe2deaae2b4c5f4bd984b17b79c Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 19:03:49 +0000 Subject: [PATCH 04/35] dts: rk3288-veyron-chromebook: dedicate npll to @@ -749,7 +749,7 @@ index 092316be67f7..e4d5c0240657 100644 2.44.0 -From 3c545b37092641715a5271525bad028d0dbd5f6f Mon Sep 17 00:00:00 2001 +From 5d07097baf8c162e2507b5f49755c43709da8578 Mon Sep 17 00:00:00 2001 From: SolidHal <hal@halemmerich.com> Date: Sun, 21 Oct 2018 16:40:15 -0500 Subject: [PATCH 05/35] Added a second reset when having an issue reading the @@ -802,7 +802,7 @@ index 3564a0f63c9c..fbfc5c628f14 100644 2.44.0 -From 984984523fc802ac95b785991d3430b9fb495062 Mon Sep 17 00:00:00 2001 +From 03d71389191efccbcf80a2cd8e9378197c694b60 Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Tue, 9 Oct 2018 22:01:07 +0200 Subject: [PATCH 06/35] block: partitions: efi: Ignore bizarre Chromebook GPT @@ -955,7 +955,7 @@ index 84b9f36b9e47..09726227e891 100644 2.44.0 -From 687418c4e4f8f814d91ea8b58a7a5ef2f1e45865 Mon Sep 17 00:00:00 2001 +From 268b4994aa6419429a0b7bbb2707f3173aeeae12 Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Tue, 30 Oct 2018 22:44:54 +0100 Subject: [PATCH 07/35] mmc: Added a flag to disable cache flush during reset @@ -1043,7 +1043,7 @@ index 62a6847a3b6f..d80cc06fa2c6 100644 2.44.0 -From 11529142cbc74b75ad0b87c70b81c438c241ba80 Mon Sep 17 00:00:00 2001 +From 418ad5f7f620b791fbf8b88f6b4ac48fbf2ae0df Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Thu, 1 Nov 2018 21:31:26 +0100 Subject: [PATCH 08/35] arm: dts: veyron: Added a flag to disable cache flush @@ -1076,7 +1076,7 @@ index d838bf0d5d9a..7aeb70e9b828 100644 2.44.0 -From 113223d4862e661cd2b7745cecaeab65301638da Mon Sep 17 00:00:00 2001 +From 9614e96657369e3b5f1942d04c4830dfc65d673e Mon Sep 17 00:00:00 2001 From: Hal Emmerich <hal@halemmerich.com> Date: Wed, 21 Aug 2019 16:52:41 -0500 Subject: [PATCH 09/35] Fix ath9k dwc2 init frame overruns @@ -1119,7 +1119,7 @@ index 0d4495c6b9f7..3444cfd35840 100644 2.44.0 -From b42e80d6f037cc9144e35db29f2ba200960a04f6 Mon Sep 17 00:00:00 2001 +From 9f406ca53f24216da1a079ac7b623bf06d7fe59a Mon Sep 17 00:00:00 2001 From: barzur <boris@konbu.org> Date: Fri, 12 Jul 2019 11:33:32 +0900 Subject: [PATCH 10/35] usb/dwc2/hcd: channel halt may not be an error @@ -1159,7 +1159,7 @@ meantime I'm including it here. 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c -index dd5b1c5691e1..e3c21829d4b3 100644 +index c1de38de2806..79ad20b3f863 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -2457,7 +2457,8 @@ static void dwc2_free_dma_aligned_buffer(struct urb *urb) @@ -1190,7 +1190,7 @@ index 5c7538d498dd..96dc5d8115d2 100644 2.44.0 -From d491de8e7fdd79fc29a0203901fbc49e6799527d Mon Sep 17 00:00:00 2001 +From be480c9ec4d70c27a16d96fd63057a4fa731af81 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 8 Oct 2019 11:03:37 +0000 Subject: [PATCH 11/35] drm/panel: edp: Extend Innolux N116BGE mode info for @@ -1237,7 +1237,7 @@ index 94fe2f3836a9..9a9e19fd1fb3 100644 2.44.0 -From c475b4332e77b0e4cce408e1a45d4751f1bf9368 Mon Sep 17 00:00:00 2001 +From 8bcecf6e4fa8daeca3336dafdb2911f86bba5821 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 8 Oct 2019 11:12:33 +0000 Subject: [PATCH 12/35] ARM: dts: rockchip: Adjust rk3288-veyron n116bge mode @@ -1276,7 +1276,7 @@ index 32c0f10765dd..ea20818202fc 100644 2.44.0 -From 3abe7ab787695dd6fddf916f86081ae99ad1c8e4 Mon Sep 17 00:00:00 2001 +From c3aa1c8a0f1d8bd7621b890e81ad246cb759e3e6 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 28 Sep 2021 20:23:13 +0300 Subject: [PATCH 13/35] Revert "clk: divider: Implement and wire up @@ -1342,7 +1342,7 @@ index a2c2b5203b0a..9a63a0447d6f 100644 2.44.0 -From 03176c8ff01e1bb5d90a8827e5e3dc8543425a31 Mon Sep 17 00:00:00 2001 +From 1294dc9566c13702b142849f4172949c7f54524a Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 25 Dec 2023 18:06:10 +0200 Subject: [PATCH 14/35] dts: veyron: bluetooth: disable dma on uart0 @@ -1370,7 +1370,7 @@ index 1cfa4eda5abf..bba671f0de4f 100644 2.44.0 -From 0bbb453f0de3012599a5632f10585b286dba4ea7 Mon Sep 17 00:00:00 2001 +From 42d49743ff8795216f587db83deee10f580d7693 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Mon, 23 Oct 2023 17:37:14 +0000 Subject: [PATCH 15/35] drm/fourcc: Add NV20 and NV30 YUV formats @@ -1420,7 +1420,7 @@ index 0f17dfa8702b..193cf8ed7912 100644 .num_planes = 3, .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 1, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index 8db7fd3f743e..3151f1fc7ebb 100644 +index 5eed091d4c29..6d6a8686c8da 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -323,6 +323,8 @@ extern "C" { @@ -1436,7 +1436,7 @@ index 8db7fd3f743e..3151f1fc7ebb 100644 2.44.0 -From 5447bf97fc3e236e40214028df9cf431b63d58ef Mon Sep 17 00:00:00 2001 +From af2ebbe72db45bff323b8d12681b3ea9d44cdd55 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Mon, 23 Oct 2023 17:37:15 +0000 Subject: [PATCH 16/35] drm/rockchip: vop: Add NV15, NV20 and NV30 support @@ -1464,7 +1464,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231023173718.188102-3-jona 3 files changed, 86 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 4b338cb89d32..ea5d96d8c55c 100644 +index a34d3fc66248..3f2ded6c032d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -280,6 +280,18 @@ static bool has_uv_swapped(uint32_t format) @@ -1548,10 +1548,10 @@ index 4b338cb89d32..ea5d96d8c55c 100644 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 5f56e0597df8..4b2daefeb8c1 100644 +index 4ea369e004a9..0cf512cc1614 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -186,6 +186,7 @@ struct vop_win_phy { +@@ -187,6 +187,7 @@ struct vop_win_phy { struct vop_reg enable; struct vop_reg gate; struct vop_reg format; @@ -1560,7 +1560,7 @@ index 5f56e0597df8..4b2daefeb8c1 100644 struct vop_reg uv_swap; struct vop_reg act_info; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 7b2805006776..f8cef0cb7bff 100644 +index f7d0edd762b3..9f03f98ab66b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -53,6 +53,26 @@ static const uint32_t formats_win_full[] = { @@ -1590,7 +1590,7 @@ index 7b2805006776..f8cef0cb7bff 100644 static const uint64_t format_modifiers_win_full[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID, -@@ -627,11 +647,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { +@@ -629,11 +649,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { static const struct vop_win_phy rk3288_win01_data = { .scl = &rk3288_win_full_scl, @@ -1605,7 +1605,7 @@ index 7b2805006776..f8cef0cb7bff 100644 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), -@@ -936,13 +957,38 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { +@@ -938,13 +959,38 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { }; @@ -1647,7 +1647,7 @@ index 7b2805006776..f8cef0cb7bff 100644 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .uv_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 15), .x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21), -@@ -965,9 +1011,9 @@ static const struct vop_win_phy rk3399_win01_data = { +@@ -967,9 +1013,9 @@ static const struct vop_win_phy rk3399_win01_data = { * AFBC on the primary plane. */ static const struct vop_win_data rk3399_vop_win_data[] = { @@ -1659,7 +1659,7 @@ index 7b2805006776..f8cef0cb7bff 100644 .type = DRM_PLANE_TYPE_OVERLAY }, { .base = 0x00, .phy = &rk3368_win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, -@@ -1099,11 +1145,11 @@ static const struct vop_intr rk3328_vop_intr = { +@@ -1101,11 +1147,11 @@ static const struct vop_intr rk3328_vop_intr = { }; static const struct vop_win_data rk3328_vop_win_data[] = { @@ -1678,7 +1678,7 @@ index 7b2805006776..f8cef0cb7bff 100644 2.44.0 -From 2a60e08a1979993dbce7ceab6c037e4f0b060e3b Mon Sep 17 00:00:00 2001 +From d88911d9aa46eac1e020399bcbf0346903bc764f Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:00 +0000 Subject: [PATCH 17/35] media: v4l2-common: Add helpers to calculate @@ -1808,7 +1808,7 @@ index 3a4b15a98e02..834b426da8b1 100644 2.44.0 -From a72596b31bcf47752e5e3de755fe5bc9d9fce355 Mon Sep 17 00:00:00 2001 +From a4b518c2b317a0b7123410b372028a2470e0178b Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:01 +0000 Subject: [PATCH 18/35] media: v4l2: Add NV15 and NV20 pixel formats @@ -2044,7 +2044,7 @@ index 78260e5d9985..79b5ef45605c 100644 2.44.0 -From 05c6970e34e5b2fa6ee73cbac268335de3977822 Mon Sep 17 00:00:00 2001 +From 236a41241df5520f6782b81b9317f997b9ede646 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:02 +0000 Subject: [PATCH 19/35] media: rkvdec: h264: Use bytesperline and buffer height @@ -2103,7 +2103,7 @@ index 4fc167b42cf0..7a1e76d423df 100644 2.44.0 -From fc2097f2b7bd123473ab9ddf43ef5881f1077d8a Mon Sep 17 00:00:00 2001 +From 42822a944cc08dad16fc6e6453357b47143c53b9 Mon Sep 17 00:00:00 2001 From: Alex Bee <knaerzche@gmail.com> Date: Sun, 5 Nov 2023 16:55:03 +0000 Subject: [PATCH 20/35] media: rkvdec: h264: Don't hardcode SPS/PPS parameters @@ -2158,7 +2158,7 @@ index 7a1e76d423df..8bce8902b8dd 100644 2.44.0 -From a33053166f12e98771cac9065a3d9d964e3d4c4a Mon Sep 17 00:00:00 2001 +From d2323f744b814829669de77849b90d56324dc3f4 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:04 +0000 Subject: [PATCH 21/35] media: rkvdec: h264: Remove SPS validation at streaming @@ -2223,7 +2223,7 @@ index 8bce8902b8dd..815d5359ddd5 100644 2.44.0 -From 17217b78f955253e88e664260865ce171678b48a Mon Sep 17 00:00:00 2001 +From 2045ad7a54dce91d909e43c7ee16f1faa0b6f081 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:05 +0000 Subject: [PATCH 22/35] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt into @@ -2293,7 +2293,7 @@ index ac398b5a9736..d1087519d218 100644 2.44.0 -From 3ead693d90f96d1ae0536d5245da582f29e3a0ff Mon Sep 17 00:00:00 2001 +From a6e6cb4caec1c63483f29fa820092e3c59b6713b Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:06 +0000 Subject: [PATCH 23/35] media: rkvdec: Move rkvdec_reset_decoded_fmt helper @@ -2381,7 +2381,7 @@ index d1087519d218..7e59db3fc24d 100644 2.44.0 -From 41220d9f4d949f76941c833c6396bee68a5b97b2 Mon Sep 17 00:00:00 2001 +From c01b75c71f136d94d8361c729fbfbcc253df2783 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:07 +0000 Subject: [PATCH 24/35] media: rkvdec: Extract decoded format enumeration into @@ -2495,7 +2495,7 @@ index 7e59db3fc24d..efbf9aa578ae 100644 2.44.0 -From 4a9ca698c526371e3363cb61a51e488315dbb9f9 Mon Sep 17 00:00:00 2001 +From 0f14d37151e406af0a7995089ca0995f4650d424 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:08 +0000 Subject: [PATCH 25/35] media: rkvdec: Add image format concept @@ -2658,7 +2658,7 @@ index 633335ebb9c4..6f8cf50c5d99 100644 2.44.0 -From ef3b58ac24467c71e766212518a5c0164b6823b1 Mon Sep 17 00:00:00 2001 +From ed9fdc54179d8067d36a9ea884f4ef46dabb6f9f Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:09 +0000 Subject: [PATCH 26/35] media: rkvdec: Add get_image_fmt ops @@ -2759,7 +2759,7 @@ index 6f8cf50c5d99..e466a2753ccf 100644 2.44.0 -From 54c30eea039b46169aa9597954980d8d7f15f26d Mon Sep 17 00:00:00 2001 +From 013bc7cfecab23db034defe59f4495704262dd34 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 16:55:10 +0000 Subject: [PATCH 27/35] media: rkvdec: h264: Support High 10 and 4:2:2 profiles @@ -2951,7 +2951,7 @@ index e466a2753ccf..9a9f4fced7a1 100644 2.44.0 -From 06018c93c09663518d521ccfbce6a9e25383da70 Mon Sep 17 00:00:00 2001 +From 176ee310a5c0706f0c0550bc4af44ffc7aab5c7a Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 23:36:08 +0000 Subject: [PATCH 28/35] media: rkvdec: Add HEVC backend @@ -5797,7 +5797,7 @@ index 9a9f4fced7a1..2f3bda1df5f0 100644 2.44.0 -From cd0936ca1b73bb7b6955fa2b56c6090f0718154f Mon Sep 17 00:00:00 2001 +From 28b00c12b9ac02b0a278eabbca053c5057ed4d36 Mon Sep 17 00:00:00 2001 From: Alex Bee <knaerzche@gmail.com> Date: Sun, 5 Nov 2023 23:36:09 +0000 Subject: [PATCH 29/35] media: rkvdec: Add variants support @@ -5939,7 +5939,7 @@ index 2f3bda1df5f0..14ce26a6c618 100644 2.44.0 -From 008039fe23bdf172678464315a9f67f8b17b46d9 Mon Sep 17 00:00:00 2001 +From ad94a4d49b91e5690eb1a986bcd63c1e2fdc5586 Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 23:36:10 +0000 Subject: [PATCH 30/35] media: rkvdec: Implement capability filtering @@ -6092,7 +6092,7 @@ index 768683747e8a..6725c5f06d10 100644 2.44.0 -From b470745edd8b27c6cf89ae3d0f1dda626a7f7157 Mon Sep 17 00:00:00 2001 +From 8a7c80574dfdec0050f3481c54fa056f2f7303e2 Mon Sep 17 00:00:00 2001 From: Alex Bee <knaerzche@gmail.com> Date: Sun, 5 Nov 2023 23:36:11 +0000 Subject: [PATCH 31/35] media: rkvdec: Add RK3288 variant @@ -6136,7 +6136,7 @@ index 6725c5f06d10..ba5812707e03 100644 2.44.0 -From a905be049d8d4fd66a5ce86f0ff4ecbbe93f0ead Mon Sep 17 00:00:00 2001 +From 4dd6d2f40fb6ad288c09b0e6cdc1df62203f9e92 Mon Sep 17 00:00:00 2001 From: Alex Bee <knaerzche@gmail.com> Date: Sun, 5 Nov 2023 23:36:12 +0000 Subject: [PATCH 32/35] media: rkvdec: Disable QoS for HEVC and VP9 on RK3328 @@ -6281,7 +6281,7 @@ index 14ce26a6c618..1d5d405da56c 100644 2.44.0 -From d6b4d44bb221187acf35465d8a0308b3478c57af Mon Sep 17 00:00:00 2001 +From 94c35e7007e361894dcdf87ad9e49e3ce0b4289b Mon Sep 17 00:00:00 2001 From: Jonas Karlman <jonas@kwiboo.se> Date: Sun, 5 Nov 2023 23:36:13 +0000 Subject: [PATCH 33/35] media: dt-bindings: rockchip,vdec: Add RK3288 @@ -6314,7 +6314,7 @@ index 08b02ec16755..0f00e9c86737 100644 2.44.0 -From 2e1e564f1fc5bdae3a295976bf2d16f71e660029 Mon Sep 17 00:00:00 2001 +From 1970789aa7240dd029db1e2c819931bcf820fc00 Mon Sep 17 00:00:00 2001 From: Alex Bee <knaerzche@gmail.com> Date: Sun, 5 Nov 2023 23:36:14 +0000 Subject: [PATCH 34/35] ARM: dts: rockchip: Add vdec node for RK3288 @@ -6367,7 +6367,7 @@ index bba671f0de4f..9065650080c1 100644 2.44.0 -From 07287aa0df640c7013fe838b3d3470e1fe59623e Mon Sep 17 00:00:00 2001 +From 0f4e70d1f8fd58f9856ac68cf1dc7bb91cc6152a Mon Sep 17 00:00:00 2001 From: "Urja (ARMLFS builder)" <urja+armlfs@urja.dev> Date: Wed, 24 Jul 2024 00:06:43 +0300 Subject: [PATCH 35/35] mfd: rk8xx: workaround veyron/ASUS C201 not powering