From dd62ce31275f1766be6400a118a0f496e076cdd2 Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Mon, 27 Aug 2018 10:30:55 +0000
Subject: [PATCH 01/34] drivers: clk-rk3288: support for dedicating NPLL to a
VOP
As controlled by the just introduced dts property.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
---
drivers/clk/rockchip/clk-rk3288.c | 70 +++++++++++++++++++++++++------
drivers/clk/rockchip/clk.h | 3 ++
2 files changed, 61 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 90d329216064a..671c786ddbaa1 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -195,10 +195,14 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
-PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
-PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
+PNAME_ED(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
+
+PNAME_ED(mux_pll_src_cgn_pll_nonvop_p) = { "cpll", "gpll", "npll" };
+PNAME_ED(mux_pll_src_cgn_pll_vop0_p) = { "cpll", "gpll", "npll" };
+PNAME_ED(mux_pll_src_cgn_pll_vop1_p) = { "cpll", "gpll", "npll" };
+
PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
-PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
+PNAME_ED(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -442,24 +446,24 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 4, GFLAGS),
- COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cgn_pll_vop0_p, 0,
RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 1, GFLAGS),
- COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cgn_pll_vop1_p, 0,
RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
RK3288_CLKGATE_CON(3), 3, GFLAGS),
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
RK3288_CLKGATE_CON(3), 12, GFLAGS),
- COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cgn_pll_nonvop_p, 0,
RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 13, GFLAGS),
- COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cgn_pll_nonvop_p, 0,
RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 14, GFLAGS),
- COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cgn_pll_nonvop_p, 0,
RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK3288_CLKGATE_CON(3), 15, GFLAGS),
@@ -468,16 +472,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
RK3288_CLKGATE_CON(5), 11, GFLAGS),
- COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cgn_pll_nonvop_p, 0,
RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 13, GFLAGS),
DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
- COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cgn_pll_nonvop_p, 0,
RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 14, GFLAGS),
- COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cgn_pll_nonvop_p, 0,
RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(13), 15, GFLAGS),
@@ -551,7 +555,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 11, GFLAGS),
- COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
+ COMPOSITE(0, "sclk_tsp", mux_pll_src_cgn_pll_nonvop_p, 0,
RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(4), 10, GFLAGS),
@@ -933,6 +937,7 @@ static void __init rk3288_common_init(struct device_node *np,
{
struct rockchip_clk_provider *ctx;
unsigned long clk_nr_clks;
+ s32 npll_vop = -1;
rk3288_cru_base = of_iomap(np, 0);
if (!rk3288_cru_base) {
@@ -940,9 +945,50 @@ static void __init rk3288_common_init(struct device_node *np,
return;
}
+ if (!of_property_read_s32(np, "rockchip,npll-for-vop", &npll_vop)) {
+ if ((npll_vop < -1) || (npll_vop > 1)) {
+ pr_warn("%s: invalid VOP to dedicate NPLL to: %d\n",
+ __func__, npll_vop);
+ } else if (npll_vop >= 0) {
+ unsigned int vop_clk_id;
+ const char ** npll_names;
+ const char ** non_npll_names;
+ int i;
+
+ /* Firstly, not-VOP needs to not use npll */
+ mux_pll_src_npll_cpll_gpll_p[0] = "dummy_npll";
+ mux_pll_src_cgn_pll_nonvop_p[2] = "dummy_npll";
+ mux_pll_src_cpll_gll_usb_npll_p[3] = "dummy_npll";
+
+ /* Then the npll VOP needs to only use npll, and the other one not use npll. */
+ if (npll_vop) {
+ vop_clk_id = DCLK_VOP1;
+ npll_names = mux_pll_src_cgn_pll_vop1_p;
+ non_npll_names = mux_pll_src_cgn_pll_vop0_p;
+ } else {
+ vop_clk_id = DCLK_VOP0;
+ npll_names = mux_pll_src_cgn_pll_vop0_p;
+ non_npll_names = mux_pll_src_cgn_pll_vop1_p;
+ }
+ npll_names[0] = "dummy_cpll";
+ npll_names[1] = "dummy_gpll";
+ non_npll_names[2] = "dummy_npll";
+
+ /* Lastly the npll-dedicated-VOP needs to be able to control npll. */
+ for (i = 0; i < ARRAY_SIZE(rk3288_clk_branches); i++) {
+ if (rk3288_clk_branches[i].id == vop_clk_id) {
+ rk3288_clk_branches[i].flags |= CLK_SET_RATE_PARENT;
+ break;
+ }
+ }
+ pr_debug("%s: npll dedicated for VOP %d\n", __func__, npll_vop);
+ }
+ }
+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3288_clk_branches,
ARRAY_SIZE(rk3288_clk_branches)) + 1;
ctx = rockchip_clk_init(np, rk3288_cru_base, clk_nr_clks);
+
if (IS_ERR(ctx)) {
pr_err("%s: rockchip clk init failed\n", __func__);
iounmap(rk3288_cru_base);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index df2b2d706450f..df85bd94647a8 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -624,6 +624,9 @@ struct clk *rockchip_clk_register_muxgrf(const char *name,
#define PNAME(x) static const char *const x[] __initconst
+/* For when you want to be able to modify the pointers. */
+#define PNAME_ED(x) static const char * x[] __initdata
+
enum rockchip_clk_branch_type {
branch_composite,
branch_mux,
--
2.44.0
From e159f5f7f349bcc4410224b5c4c131270f40662f Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Wed, 22 Aug 2018 18:36:40 +0000
Subject: [PATCH 02/34] drm: dw_hdmi-rockchip: better clock selection logic and
dts-based rate list
This contains traces of the following commits from the ChromeOS 3.14
tree, which improve RF/EMI performance and detach the clock selection
logic from the HDMI PHY configurations, plus support for configuring
the allowed clock rates via device tree as they are dependent on
PLL configuration and maybe even the PCB layout and other hardware things,
eg. interference to wifi or such (EMI).
Rates that were allowed previous to this patch are added as the fallback
list if no dts configuration exists.
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Adjust rockchip_mpll_cfg for 146.25
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: expand the informal mpll config
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: add slop to more tables
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: redo rockchip hdmi to allow slop
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Use auto-generated tables
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Fixup the clock to be what we expect
CHROMIUM: drm/rockchip: hdmi: adjust cklvl & txlvl for RF/EMI
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Set cur_ctr to 0 always
CHROMIUM: drm: rockchip/dw_hdmi-rockchip: Decrease slop
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 136 ++++++++++++++++----
1 file changed, 109 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index f737e7d46e667..0bd62f21d6e57 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -81,8 +81,13 @@ struct rockchip_hdmi {
struct clk *grf_clk;
struct dw_hdmi *hdmi;
struct phy *phy;
+ u32* rates;
+ u32 rates_cnt;
};
+#define CLK_SLOP(clk) ((clk) / 1000)
+#define CLK_PLUS_SLOP(clk) ((clk) + CLK_SLOP(clk))
+
static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
{
struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
@@ -90,6 +95,23 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder)
return container_of(rkencoder, struct rockchip_hdmi, encoder);
}
+/* These were the rates allowed by the driver before rates list in device tree,
+ * so keep them around as a fallback */
+static const u32 dw_hdmi_fallback_rates[] = {
+ 27000000,
+ 36000000,
+ 40000000,
+ 54000000,
+ 65000000,
+ 66000000,
+ 74250000,
+ 83500000,
+ 106500000,
+ 108000000,
+ 146250000,
+ 148500000
+};
+
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
{
30666000, {
@@ -179,7 +201,7 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
};
static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
- /* pixelclk bpp8 bpp10 bpp12 */
+ /* pixelclk bpp8 bpp10 bpp12 */
{
600000000, { 0x0000, 0x0000, 0x0000 },
}, {
@@ -188,18 +210,18 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
};
static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
- /*pixelclk symbol term vlev*/
- { 74250000, 0x8009, 0x0004, 0x0272},
- { 165000000, 0x802b, 0x0004, 0x0209},
- { 297000000, 0x8039, 0x0005, 0x028d},
- { 594000000, 0x8039, 0x0000, 0x019d},
- { ~0UL, 0x0000, 0x0000, 0x0000}
+ /*pixelclk symbol term vlev*/
+ { CLK_PLUS_SLOP(74250000), 0x8009, 0x0004, 0x0272},
+ { CLK_PLUS_SLOP(165000000), 0x802b, 0x0004, 0x0209},
+ { CLK_PLUS_SLOP(297000000), 0x8039, 0x0005, 0x028d},
+ { ~0UL, 0x0000, 0x0000, 0x0000}
};
static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
{
struct device_node *np = hdmi->dev->of_node;
int ret;
+ int rates_cnt;
hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
if (IS_ERR(hdmi->regmap)) {
@@ -231,34 +253,58 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
return ret;
ret = devm_regulator_get_enable(hdmi->dev, "avdd-1v8");
+ if (ret)
+ return ret;
- return ret;
+ if ((rates_cnt = of_property_count_u32_elems(np, "rockchip,hdmi-rates-hz")) > 0) {
+ int rv;
+ u32 *rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL);
+ if (!rates)
+ return -ENOMEM;
+ rv = of_property_read_u32_array(np, "rockchip,hdmi-rates-hz", rates, rates_cnt);
+ if (rv)
+ return rv;
+ hdmi->rates = rates;
+ hdmi->rates_cnt = rates_cnt;
+ } else {
+ rates_cnt = ARRAY_SIZE(dw_hdmi_fallback_rates);
+ hdmi->rates = devm_kmalloc_array(hdmi->dev, rates_cnt, sizeof(u32), GFP_KERNEL);
+ if (!hdmi->rates)
+ return -ENOMEM;
+ memcpy(hdmi->rates, dw_hdmi_fallback_rates, rates_cnt * sizeof(u32));
+ hdmi->rates_cnt = rates_cnt;
+ }
+
+ return 0;
}
static enum drm_mode_status
-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
- const struct drm_display_info *info,
+dw_hdmi_rockchip_encoder_mode_valid(struct drm_encoder *encoder,
const struct drm_display_mode *mode)
{
- struct rockchip_hdmi *hdmi = data;
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
int pclk = mode->clock * 1000;
+ int num_rates = hdmi->rates_cnt;
+ int i;
if (hdmi->chip_data->max_tmds_clock &&
mode->clock > hdmi->chip_data->max_tmds_clock)
return MODE_CLOCK_HIGH;
- if (hdmi->ref_clk) {
- int rpclk = clk_round_rate(hdmi->ref_clk, pclk);
-
- if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000)
- return MODE_NOCLOCK;
- }
+ /*
+ * Pixel clocks we support are always < 2GHz and so fit in an
+ * int. We should make sure source rate does too so we don't get
+ * overflow when we multiply by 1000.
+ */
+ if (mode->clock > INT_MAX / 1000)
+ return MODE_BAD;
- if (hdmi->hdmiphy_clk) {
- int rpclk = clk_round_rate(hdmi->hdmiphy_clk, pclk);
+ for (i = 0; i < num_rates; i++) {
+ int slop = CLK_SLOP(pclk);
- if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000)
- return MODE_NOCLOCK;
+ if ((pclk >= hdmi->rates[i] - slop) &&
+ (pclk <= hdmi->rates[i] + slop))
+ return MODE_OK;
}
return MODE_OK;
@@ -273,7 +319,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adj_mode)
{
- return true;
+ struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ int pclk = adj_mode->clock * 1000;
+ int best_diff = INT_MAX;
+ int best_clock = 0;
+ int slop;
+ int i;
+
+ /* Pick the best clock */
+ for (i = 0; i < hdmi->rates_cnt; i++) {
+ int diff = hdmi->rates[i] - pclk;
+
+ if (diff < 0)
+ diff = -diff;
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_clock = hdmi->rates[i];
+
+ /* Bail early if we're exact */
+ if (best_diff == 0)
+ return true;
+ }
+ }
+
+ /* Double check that it's OK */
+ slop = CLK_SLOP(pclk);
+ if ((pclk >= best_clock - slop) && (pclk <= best_clock + slop)) {
+ adj_mode->clock = DIV_ROUND_UP(best_clock, 1000);
+ return true;
+ }
+
+ /* Shoudn't be here; we should have said rate wasn't valid */
+ dev_warn(hdmi->dev, "tried to set invalid rate %d\n", adj_mode->clock);
+ return false;
}
static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
@@ -328,6 +406,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
}
static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
+ .mode_valid = dw_hdmi_rockchip_encoder_mode_valid,
.mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
.mode_set = dw_hdmi_rockchip_encoder_mode_set,
.enable = dw_hdmi_rockchip_encoder_enable,
@@ -433,7 +512,9 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = {
};
static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
+ .mpll_cfg = rockchip_mpll_cfg,
+ .cur_ctr = rockchip_cur_ctr,
+ .phy_config = rockchip_phy_config,
.phy_data = &rk3228_chip_data,
.phy_ops = &rk3228_hdmi_phy_ops,
.phy_name = "inno_dw_hdmi_phy2",
@@ -448,7 +529,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = {
};
static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -469,7 +549,9 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = {
};
static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
+ .mpll_cfg = rockchip_mpll_cfg,
+ .cur_ctr = rockchip_cur_ctr,
+ .phy_config = rockchip_phy_config,
.phy_data = &rk3328_chip_data,
.phy_ops = &rk3328_hdmi_phy_ops,
.phy_name = "inno_dw_hdmi_phy2",
@@ -485,7 +567,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = {
};
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -499,7 +580,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = {
};
static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
.mpll_cfg = rockchip_mpll_cfg,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
@@ -622,6 +702,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return 0;
err_bind:
+ devm_kfree(hdmi->dev, hdmi->rates);
drm_encoder_cleanup(encoder);
return ret;
@@ -632,6 +713,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
{
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
+ devm_kfree(hdmi->dev, hdmi->rates);
dw_hdmi_unbind(hdmi->hdmi);
drm_encoder_cleanup(&hdmi->encoder.encoder);
}
--
2.44.0
From 6ee44a87817d32be0207ce1583f3ce81ffb68608 Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Mon, 27 Aug 2018 19:00:50 +0000
Subject: [PATCH 03/34] dts: rk3288: support for dedicating npll to a vop
Add the VOP DCLKs to the assigned clocks list so their
parents can be set in the dts include files for
devices that do dedicate npll to a vop.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 3f1d640afafae..2992c323d5554 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -876,12 +876,14 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
<&cru PCLK_PERI>;
- assigned-clock-rates = <594000000>, <400000000>,
+ assigned-clock-rates = <0>, <0>,
+ <594000000>, <400000000>,
<500000000>, <300000000>,
<150000000>, <75000000>,
<300000000>, <150000000>,
--
2.44.0
From e253242062b4732d53fe2c176520cdf0c6415d9b Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Mon, 27 Aug 2018 19:03:49 +0000
Subject: [PATCH 04/34] dts: rk3288-veyron-chromebook: dedicate npll to
VOP0/HDMI + HDMI rates
This enables flexible HDMI rates on the rk3288 chromebooks so that they
actually work with displays (also others than a 1080p one) in the wild.
The frequency list matches what ChromeOS allows.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
---
.../rockchip/rk3288-veyron-chromebook.dtsi | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi
index 3677571b4d827..b61a4b0d7015b 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi
@@ -83,6 +83,68 @@
};
};
+&cru {
+ /* Dedicate NPLL for VOP0 / VOP_BIG for HDMI. */
+ rockchip,npll-for-vop = <0>;
+ /* The first assigned clocks are DCLK_VOP0 and DCLK_VOP1 */
+ assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
+};
+
+/* Delete the nodes that allow non-desirable VOP - connector links. That
+ * is the eDP cannot use vopb and HDMI cannot use vopl. */
+
+/delete-node/ &edp_in_vopb;
+/delete-node/ &vopb_out_edp;
+/delete-node/ &hdmi_in_vopl;
+/delete-node/ &vopl_out_hdmi;
+
+&hdmi {
+ /* These depend on NPLL being dedicated to HDMI use. */
+ rockchip,hdmi-rates-hz = <
+ 25176471 /* for 25.175 MHz, 0.006% off */
+ 25200000
+ 27000000
+ 28320000
+ 30240000
+ 31500000
+ 32000000
+ 33750000
+ 36000000
+ 40000000
+ 49500000
+ 50000000
+ 54000000
+ 57290323 /* for 57.284 MHz, .011 % off */
+ 65000000
+ 68250000
+ 71000000
+ 72000000
+ 73250000
+ 74250000
+ 74437500 /* for 74.44 MHz, .003% off */
+ 75000000
+ 78750000
+ 78800000
+ 79500000
+ 83500000
+ 85500000
+ 88750000
+ 97750000
+ 101000000
+ 106500000
+ 108000000
+ 115500000
+ 118666667 /* for 118.68 MHz, .011% off */
+ 119000000
+ 121714286 /* for 121.75 MHz, .029% off */
+ 135000000
+ 136800000 /* for 136.75 MHz, .037% off */
+ 146250000
+ 148500000
+ 154000000
+ 162000000 >;
+};
+
&rk808 {
vcc11-supply = <&vcc_5v>;
--
2.44.0
From 49cb9e40c6000858dcbdb08a9df03c91f032ba2a Mon Sep 17 00:00:00 2001
From: SolidHal <hal@halemmerich.com>
Date: Sun, 21 Oct 2018 16:40:15 -0500
Subject: [PATCH 05/34] Added a second reset when having an issue reading the
emmc.
The c201 emmc can be... touchy. Sometimes one full reset isn't
enough to get it into a wokring state if it found it's way into
a really bad state. Note that in my testing WITHOUT this patch,
this only happens about once in just over 1600 reboots.
--
Edited by Urja Rannikko to actually limit the retries to once,
and to apply to 4.20.
--
Signed-off-by: SolidHal <hal@halemmerich.com>
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
---
drivers/mmc/core/block.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c
index 4830628510e6e..7658effcb6efe 100644
--- a/drivers/mmc/core/block.c
+++ b/drivers/mmc/core/block.c
@@ -1090,6 +1090,7 @@ static unsigned int mmc_blk_data_timeout_ms(struct mmc_host *host,
static int mmc_blk_reset(struct mmc_blk_data *md, struct mmc_host *host,
int type)
{
+ int retries = 1;
int err;
struct mmc_blk_data *main_md = dev_get_drvdata(&host->card->dev);
@@ -1097,7 +1098,14 @@ static int mmc_blk_reset(struct mmc_blk_data *md, struct mmc_host *host,
return -EEXIST;
md->reset_done |= type;
+retry:
err = mmc_hw_reset(host->card);
+
+ /* Retry once because the C201 eMMC can be touchy */
+ if ((err) && (retries--)) {
+ goto retry;
+ }
+
/*
* A successful reset will leave the card in the main partition, but
* upon failure it might not be, so set it to MMC_BLK_PART_INVALID
--
2.44.0
From dd661291f5d3c6f0b7570d35c71d2373b0c3049f Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Tue, 9 Oct 2018 22:01:07 +0200
Subject: [PATCH 06/34] block: partitions: efi: Ignore bizarre Chromebook GPT
partitions
This patch is based on @SolidHal work here :
https://raw.githubusercontent.com/SolidHal/PrawnOS/master/resources/BuildResources/patches-tested/kernel/0001-block-partitions-efi-Add-support-for-IGNOREME-GPT-si.patch
Here's the initial commit message :
8<---
This patch adds support for a special GPT header signature marker (using
the string 'IGNOREME' instead of the spec's 'EFI PART'). This tells the
kernel to ignore this GPT completely and look at the other one instead.
Since the kernel always prefers the primary GPT anyway, all we really
need to do effectively is to check whether the primary GPT is marked
'IGNOREME' and force evaluation of the secondary one in that case.
Borrowed from the chrome os 3.14 kernel, the commit can be found here:
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/abba28d0a1b7361da6e2023352e92687166ca30d
Also bundled in this commit
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/bd0c62c7de0c8a63314b7955e5718d8f6192f9d2%5E%21/#F0
Which is a small compiler warning fix for the above patch
This patch fixes how the kernel detects and handles certain mmc
manufatures devices, and allows the partitions on the mmc to be bootable
and mountable.
>8---
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
block/partitions/efi.c | 33 +++++++++++++++++++++++----------
block/partitions/efi.h | 3 ++-
2 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/block/partitions/efi.c b/block/partitions/efi.c
index 7acba66eed481..087032a4705e7 100644
--- a/block/partitions/efi.c
+++ b/block/partitions/efi.c
@@ -328,23 +328,34 @@ static gpt_header *alloc_read_gpt_header(struct parsed_partitions *state,
* @lba: logical block address of the GPT header to test
* @gpt: GPT header ptr, filled on return.
* @ptes: PTEs ptr, filled on return.
+ * @ignored is filled on return with 1 if this is an IGNOREME GPT,
+ * 0 otherwise. May be NULL.
*
* Description: returns 1 if valid, 0 on error.
* If valid, returns pointers to newly allocated GPT header and PTEs.
*/
static int is_gpt_valid(struct parsed_partitions *state, u64 lba,
- gpt_header **gpt, gpt_entry **ptes)
+ gpt_header **gpt, gpt_entry **ptes, int *ignored)
{
u32 crc, origcrc;
u64 lastlba, pt_size;
+ if (ignored)
+ *ignored = 0;
if (!ptes)
return 0;
if (!(*gpt = alloc_read_gpt_header(state, lba)))
return 0;
/* Check the GUID Partition Table signature */
- if (le64_to_cpu((*gpt)->signature) != GPT_HEADER_SIGNATURE) {
+
+ if (le64_to_cpu((*gpt)->signature) == GPT_HEADER_SIGNATURE_IGNORED) {
+ pr_debug("GUID Partition Table at LBA %llu marked IGNOREME\n",
+ (unsigned long long)lba);
+ if (ignored)
+ *ignored = 1;
+ goto fail;
+ } else if (le64_to_cpu((*gpt)->signature) != GPT_HEADER_SIGNATURE) {
pr_debug("GUID Partition Table Header signature is wrong:"
"%lld != %lld\n",
(unsigned long long)le64_to_cpu((*gpt)->signature),
@@ -581,7 +592,7 @@ compare_gpts(gpt_header *pgpt, gpt_header *agpt, u64 lastlba)
static int find_valid_gpt(struct parsed_partitions *state, gpt_header **gpt,
gpt_entry **ptes)
{
- int good_pgpt = 0, good_agpt = 0, good_pmbr = 0;
+ int good_pgpt = 0, good_agpt = 0, good_pmbr = 0, pgpt_ignored = 0;
gpt_header *pgpt = NULL, *agpt = NULL;
gpt_entry *pptes = NULL, *aptes = NULL;
legacy_mbr *legacymbr;
@@ -613,13 +624,13 @@ static int find_valid_gpt(struct parsed_partitions *state, gpt_header **gpt,
}
good_pgpt = is_gpt_valid(state, GPT_PRIMARY_PARTITION_TABLE_LBA,
- &pgpt, &pptes);
+ &pgpt, &pptes, &pgpt_ignored);
if (good_pgpt)
good_agpt = is_gpt_valid(state,
le64_to_cpu(pgpt->alternate_lba),
- &agpt, &aptes);
- if (!good_agpt && force_gpt)
- good_agpt = is_gpt_valid(state, lastlba, &agpt, &aptes);
+ &agpt, &aptes, NULL);
+ if (!good_agpt && (force_gpt || pgpt_ignored))
+ good_agpt = is_gpt_valid(state, lastlba, &agpt, &aptes, NULL);
if (!good_agpt && force_gpt && fops->alternative_gpt_sector) {
sector_t agpt_sector;
@@ -628,14 +639,15 @@ static int find_valid_gpt(struct parsed_partitions *state, gpt_header **gpt,
err = fops->alternative_gpt_sector(disk, &agpt_sector);
if (!err)
good_agpt = is_gpt_valid(state, agpt_sector,
- &agpt, &aptes);
+ &agpt, &aptes, NULL);
}
/* The obviously unsuccessful case */
if (!good_pgpt && !good_agpt)
goto fail;
- compare_gpts(pgpt, agpt, lastlba);
+ if (!pgpt_ignored)
+ compare_gpts(pgpt, agpt, lastlba);
/* The good cases */
if (good_pgpt) {
@@ -652,7 +664,8 @@ static int find_valid_gpt(struct parsed_partitions *state, gpt_header **gpt,
*ptes = aptes;
kfree(pgpt);
kfree(pptes);
- pr_warn("Primary GPT is invalid, using alternate GPT.\n");
+ pr_warn("Primary GPT is %s, using alternate GPT.\n",
+ pgpt_ignored ? "being ignored" : "invalid");
return 1;
}
diff --git a/block/partitions/efi.h b/block/partitions/efi.h
index 84b9f36b9e479..09726227e8913 100644
--- a/block/partitions/efi.h
+++ b/block/partitions/efi.h
@@ -26,7 +26,8 @@
#define GPT_MBR_PROTECTIVE 1
#define GPT_MBR_HYBRID 2
-#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
+#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL /* 'EFI PART' */
+#define GPT_HEADER_SIGNATURE_IGNORED 0x454d45524f4e4749ULL /* 'IGNOREME' */
#define GPT_HEADER_REVISION_V1 0x00010000
#define GPT_PRIMARY_PARTITION_TABLE_LBA 1
--
2.44.0
From 768e34931802fe87e75c79d3eb6c65381c2760fb Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Tue, 30 Oct 2018 22:44:54 +0100
Subject: [PATCH 07/34] mmc: Added a flag to disable cache flush during reset
The ASUS Chromebook suffer from 10 minutes long hang, when trying
to flush the cache of the eMMC, in order to recover from eMMC init
issues when booting the system.
A new flag "no-recovery-cache-flush" whose purpose is to disable
cache flush during recovery reset, has been added.
This work is adapted from @SolidHal work, which is available here :
https://github.com/SolidHal/PrawnOS/blob/develop-4.19/resources/BuildResources/patches-tested/kernel/Don-t-try-to-flush-cache-on-reset.patch
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
drivers/mmc/core/host.c | 2 ++
drivers/mmc/core/mmc.c | 18 ++++++++++++++----
include/linux/mmc/host.h | 1 +
3 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index dacb5bd9bb714..04703ce624abe 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -405,6 +405,8 @@ int mmc_of_parse(struct mmc_host *host)
if (device_property_read_bool(dev, "no-mmc-hs400"))
host->caps2 &= ~(MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V |
MMC_CAP2_HS400_ES);
+ if (device_property_read_bool(dev, "no-recovery-cache-flush"))
+ host->caps2 |= MMC_CAP2_NO_RECOVERY_CACHE_FLUSH;
/* Must be after "non-removable" check */
if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) {
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 1522fd2b517dd..0a970bc258f23 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -2242,6 +2242,12 @@ static int mmc_runtime_resume(struct mmc_host *host)
return 0;
}
+static inline int mmc_can_flush_during_recovery(
+ struct mmc_host *host)
+{
+ return (host->caps2 & MMC_CAP2_NO_RECOVERY_CACHE_FLUSH) == 0;
+}
+
static int mmc_can_reset(struct mmc_card *card)
{
u8 rst_n_function;
@@ -2256,11 +2262,15 @@ static int _mmc_hw_reset(struct mmc_host *host)
{
struct mmc_card *card = host->card;
- /*
- * In the case of recovery, we can't expect flushing the cache to work
- * always, but we have a go and ignore errors.
+ /* Using a "Cache flush" during recovery events seems...
+ * "dubious" at best, and generate significant issues on
+ * some platforms, like 10 minutes hang up, at worst.
+ * I'm keeping this line because the old code did it but...
+ * feel free to double check if that's needed at all.
*/
- _mmc_flush_cache(host);
+
+ if (mmc_can_flush_during_recovery(host))
+ _mmc_flush_cache(host);
if ((host->caps & MMC_CAP_HW_RESET) && host->ops->card_hw_reset &&
mmc_can_reset(card)) {
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 68f09a955a902..eb7dbf0f9b101 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -459,6 +459,7 @@ struct mmc_host {
#define MMC_CAP2_CRYPTO 0
#endif
#define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */
+#define MMC_CAP2_NO_RECOVERY_CACHE_FLUSH (1 << 29) /* Do not flush the device cache when recovering */
bool uhs2_sd_tran; /* UHS-II flag for SD_TRAN state */
bool uhs2_app_cmd; /* UHS-II flag for APP command */
--
2.44.0
From eeea2103586d5cd29bd94f863c7be3c2d5cf945c Mon Sep 17 00:00:00 2001
From: "Miouyouyou (Myy)" <myy@miouyouyou.fr>
Date: Thu, 1 Nov 2018 21:31:26 +0100
Subject: [PATCH 08/34] arm: dts: veyron: Added a flag to disable cache flush
during reset
Flushing the MMC cache of ASUS Chromebooks during initialization or
"recovery" generates 10 minutes hangup, according to @SolidHal.
This is an adaptation of @SolidHal, in order to pinpoint the fix to
Veyron Chromebooks, and avoiding issues other RK3288 boards.
Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr>
---
arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
index 260d6c92cfd11..08ce8bfb70b21 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi
@@ -157,6 +157,7 @@
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
non-removable;
+ no-recovery-cache-flush;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
};
--
2.44.0
From ef81b07b65f1112cddb99d9c5a6e9e549f892001 Mon Sep 17 00:00:00 2001
From: Hal Emmerich <hal@halemmerich.com>
Date: Wed, 21 Aug 2019 16:52:41 -0500
Subject: [PATCH 09/34] Fix ath9k dwc2 init frame overruns
[ by Urja Rannikko: changed to log message to something more sensible. ]
This is a workaround for ar9271 drvices using the open ath9k firmware
With the dwc2 usb driver these endpoints end up throwing piles of
frame overrun errors and prevent the ath9k firmware from communicating
properly with the c201
This fix elongates the microframes by 4 so the dwc2 and ath9k devices
communicate properly. In my testing this did not impact network speeds.
---
drivers/usb/dwc2/hcd_queue.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
index b0098792dd225..73d7c7754bc57 100644
--- a/drivers/usb/dwc2/hcd_queue.c
+++ b/drivers/usb/dwc2/hcd_queue.c
@@ -1491,6 +1491,16 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
device_ns += dwc_tt->usb_tt->think_time;
qh->device_us = NS_TO_US(device_ns);
+ //Only enable workaround for highspeed devices, since only low and full speed devices so split, we can just check split
+ //The packets that fail right after the firmware is transferred are on an interrupt ep so we can use that to further narrow it down
+ //The ath9k device has issues with ep 3 and ep4
+ if(!do_split && !ep_is_isoc && ep_is_int && (urb->pipe_info.ep_num == 3 || urb->pipe_info.ep_num == 4)){
+ if (urb->interval == 1){
+ urb->interval = 4;
+ dev_info(hsotg->dev, "ath9k workaround: set usb urb interval to %d\n", urb->interval);
+ }
+ }
+
qh->device_interval = urb->interval;
qh->host_interval = urb->interval * (do_split ? 8 : 1);
--
2.44.0
From d95ec6da73b14c9fa4d822983eb5eba184d5be86 Mon Sep 17 00:00:00 2001
From: barzur <boris@konbu.org>
Date: Fri, 12 Jul 2019 11:33:32 +0900
Subject: [PATCH 10/34] usb/dwc2/hcd: channel halt may not be an error
Truncating the data was causing null pointer exceptions in memcpy,
let's be more careful.
Addendum by Urja Rannikko:
This was reported as a pull request on my linux github repo and it came
with this reproducer & notes:
-- begin --
I sometimes get kernel oops when USB tethering.
Here is how to repro:
* create high load on the CPU: I build a kernel with -j6;
* saturate your cdc_ether connection to the phone (I use netcat on both sides
to do so, with termux on android);
I tracked down the issue to buffers getting truncated, the driver extracting
a target address from the end of the buffer (weird) & memcpy to a non validated
address.
I've fixed it by validating the address we write to & stopped treating
un-explained channel closure as errors. I guess the channel is closed due to a
timeout (maybe?), caused by heavy context switching on the machine.
I've been testing the following patch for ~1 week and it seems to work well.
-- end --
I do not have a suitable phone to reproduce this with so I cant personally
say if it works and I dont 100% understand it, but I looked at the patch
and I think it looks okay-ish (tho maybe should be two patches), so in the
meantime I'm including it here.
---
drivers/usb/dwc2/hcd.c | 3 ++-
drivers/usb/dwc2/hcd_intr.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 60ef8092259a9..a190524108e85 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -2457,7 +2457,8 @@ static void dwc2_free_dma_aligned_buffer(struct urb *urb)
else
length = urb->actual_length;
- memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
+ if (stored_xfer_buffer)
+ memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
}
kfree(urb->transfer_buffer);
urb->transfer_buffer = stored_xfer_buffer;
diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c
index 5c7538d498dd1..96dc5d8115d2c 100644
--- a/drivers/usb/dwc2/hcd_intr.c
+++ b/drivers/usb/dwc2/hcd_intr.c
@@ -1935,7 +1935,8 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
"hcint 0x%08x, intsts 0x%08x\n",
chan->hcint,
dwc2_readl(hsotg, GINTSTS));
- goto error;
+ dwc2_halt_channel(hsotg, chan, qtd,
+ DWC2_HC_XFER_PERIODIC_INCOMPLETE);
}
}
} else {
--
2.44.0
From e683db973eb4444218817faaeeb9692a0090c1b5 Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Tue, 8 Oct 2019 11:03:37 +0000
Subject: [PATCH 11/34] drm/panel: edp: Extend Innolux N116BGE mode info for
~60Hz from 74.25 Mhz
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
---
drivers/gpu/drm/panel/panel-edp.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
index 52028c8f8988d..cc29548273c2d 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/panel-edp.c
@@ -1295,16 +1295,25 @@ static const struct panel_desc innolux_n116bca_ea1 = {
* porch, back porch, or sync length. For now we'll leave a single setting
* here which allows a bit of tweaking of the pixel clock at the expense of
* refresh rate.
+ *
+ * Experimental testing with one panel suggests that the split among
+ * front/back/sync is not important, but the panel is not stable
+ * at htotal less than 1520 (atleast when running at 74.25 Mhz).
+ *
+ * There exists an experimental mode that gives very close to 60 Hz mode
+ * from 74.25 Mhz with htotal 1543 and vtotal 802 - we allow the
+ * hfront_porch and vback_porch to be adjusted to reach that mode.
+ *
*/
static const struct display_timing innolux_n116bge_timing = {
.pixelclock = { 72600000, 76420000, 80240000 },
.hactive = { 1366, 1366, 1366 },
- .hfront_porch = { 136, 136, 136 },
+ .hfront_porch = { 87, 136, 136 },
.hback_porch = { 60, 60, 60 },
.hsync_len = { 30, 30, 30 },
.vactive = { 768, 768, 768 },
.vfront_porch = { 8, 8, 8 },
- .vback_porch = { 12, 12, 12 },
+ .vback_porch = { 12, 12, 14 },
.vsync_len = { 12, 12, 12 },
.flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW,
};
--
2.44.0
From b16317c0cdfbfca126d8ff33052b105d12efeb41 Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Tue, 8 Oct 2019 11:12:33 +0000
Subject: [PATCH 12/34] ARM: dts: rockchip: Adjust rk3288-veyron n116bge mode
for ~60Hz
This is an experimental mode that gets very close to 60Hz (60.00067..)
from the available clock of 74.25Mhz on an rk3288. The mode
has htotal 1543 and vtotal 802.
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
---
arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi
index fb031964fa2bb..128176b7c3721 100644
--- a/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi
@@ -62,13 +62,13 @@
panel-timing {
clock-frequency = <74250000>;
hactive = <1366>;
- hfront-porch = <136>;
+ hfront-porch = <87>;
hback-porch = <60>;
hsync-len = <30>;
hsync-active = <0>;
vactive = <768>;
vfront-porch = <8>;
- vback-porch = <12>;
+ vback-porch = <14>;
vsync-len = <12>;
vsync-active = <0>;
};
--
2.44.0
From 26580545bf83cd538649fe24a981a3e51e88a916 Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Mon, 25 Dec 2023 18:06:10 +0200
Subject: [PATCH 13/34] dts: veyron: bluetooth: disable dma on uart0
I just pulled this off the internet ;)
https://codeberg.org/petms/linux-veyron-patches-and-apkbuild
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 2992c323d5554..949bc1829c8fa 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -387,8 +387,6 @@
reg-io-width = <4>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
- dmas = <&dmac_peri 1>, <&dmac_peri 2>;
- dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer>;
status = "disabled";
--
2.44.0
From 0b4946cbbe37c7410c74fc33852dd01b187cdc1a Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:00 +0000
Subject: [PATCH 14/34] media: v4l2-common: Add helpers to calculate
bytesperline and sizeimage
Add helper functions to calculate plane bytesperline and sizeimage,
these new helpers consider bpp div, block width and height when
calculating plane bytesperline and sizeimage.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/media/v4l2-core/v4l2-common.c | 78 +++++++++++++--------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index e4b2de3833ee3..d9b0766f3073f 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -357,6 +357,34 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
return info->block_h[plane];
}
+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane,
+ unsigned int width)
+{
+ unsigned int hdiv = plane ? info->hdiv : 1;
+ unsigned int aligned_width =
+ ALIGN(width, v4l2_format_block_width(info, plane));
+
+ return DIV_ROUND_UP(aligned_width, hdiv) *
+ info->bpp[plane] / info->bpp_div[plane];
+}
+
+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
+ unsigned int height)
+{
+ unsigned int vdiv = plane ? info->vdiv : 1;
+ unsigned int aligned_height =
+ ALIGN(height, v4l2_format_block_height(info, plane));
+
+ return DIV_ROUND_UP(aligned_height, vdiv);
+}
+
+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
+ unsigned int width, unsigned int height)
+{
+ return v4l2_format_plane_width(info, plane, width) *
+ v4l2_format_plane_height(info, plane, height);
+}
+
void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
const struct v4l2_frmsize_stepwise *frmsize)
{
@@ -392,37 +420,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
if (info->mem_planes == 1) {
plane = &pixfmt->plane_fmt[0];
- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0];
+ plane->bytesperline = v4l2_format_plane_width(info, 0, width);
plane->sizeimage = 0;
- for (i = 0; i < info->comp_planes; i++) {
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
- unsigned int aligned_width;
- unsigned int aligned_height;
-
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
-
- plane->sizeimage += info->bpp[i] *
- DIV_ROUND_UP(aligned_width, hdiv) *
- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i];
- }
+ for (i = 0; i < info->comp_planes; i++)
+ plane->sizeimage +=
+ v4l2_format_plane_size(info, i, width, height);
} else {
for (i = 0; i < info->comp_planes; i++) {
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
- unsigned int aligned_width;
- unsigned int aligned_height;
-
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
-
plane = &pixfmt->plane_fmt[i];
plane->bytesperline =
- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv) / info->bpp_div[i];
- plane->sizeimage =
- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv);
+ v4l2_format_plane_width(info, i, width);
+ plane->sizeimage = plane->bytesperline *
+ v4l2_format_plane_height(info, i, height);
}
}
return 0;
@@ -446,22 +456,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
pixfmt->width = width;
pixfmt->height = height;
pixfmt->pixelformat = pixelformat;
- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0];
+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width);
pixfmt->sizeimage = 0;
- for (i = 0; i < info->comp_planes; i++) {
- unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
- unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
- unsigned int aligned_width;
- unsigned int aligned_height;
-
- aligned_width = ALIGN(width, v4l2_format_block_width(info, i));
- aligned_height = ALIGN(height, v4l2_format_block_height(info, i));
-
- pixfmt->sizeimage += info->bpp[i] *
- DIV_ROUND_UP(aligned_width, hdiv) *
- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i];
- }
+ for (i = 0; i < info->comp_planes; i++)
+ pixfmt->sizeimage +=
+ v4l2_format_plane_size(info, i, width, height);
return 0;
}
EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
--
2.44.0
From 3528d19ca2a6c6ac9e4bc04015e7550594666c81 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:01 +0000
Subject: [PATCH 15/34] media: v4l2: Add NV15 and NV20 pixel formats
Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for
10-bit buffers.
NV15 and NV20 is 10-bit 4:2:0/4:2:2 semi-planar YUV formats similar to
NV12 and NV16, using 10-bit components with no padding between each
component. Instead, a group of 4 luminance/chrominance samples are
stored over 5 bytes in little endian order:
YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
The '15' and '20' suffix refers to the optimum effective bits per pixel
which is achieved when the total number of luminance samples is a
multiple of 8 for NV15 and 4 for NV20.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../media/v4l/pixfmt-yuv-planar.rst | 128 ++++++++++++++++++
drivers/media/v4l2-core/v4l2-common.c | 2 +
drivers/media/v4l2-core/v4l2-ioctl.c | 2 +
include/uapi/linux/videodev2.h | 2 +
4 files changed, 134 insertions(+)
diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
index b788f69338554..22cad8c9726bf 100644
--- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
+++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
@@ -79,6 +79,13 @@ All components are stored with the same number of bits per component.
- Cr, Cb
- Yes
- Linear
+ * - V4L2_PIX_FMT_NV15
+ - 'NV15'
+ - 10
+ - 4:2:0
+ - Cb, Cr
+ - Yes
+ - Linear
* - V4L2_PIX_FMT_NV12M
- 'NM12'
- 8
@@ -172,6 +179,13 @@ All components are stored with the same number of bits per component.
- Cr, Cb
- Yes
- Linear
+ * - V4L2_PIX_FMT_NV20
+ - 'NV20'
+ - 10
+ - 4:2:2
+ - Cb, Cr
+ - Yes
+ - Linear
* - V4L2_PIX_FMT_NV16M
- 'NM16'
- 8
@@ -302,6 +316,57 @@ of the luma plane.
- Cr\ :sub:`11`
+.. _V4L2-PIX-FMT-NV15:
+
+NV15
+----
+
+Semi-planar 10-bit YUV 4:2:0 format similar to NV12, using 10-bit components
+with no padding between each component. A group of 4 components are stored over
+5 bytes in little endian order.
+
+.. flat-table:: Sample 4x4 NV15 Image (1 byte per cell)
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - Y'\ :sub:`00[7:0]`
+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]`
+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]`
+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]`
+ - Y'\ :sub:`03[9:2]`
+ * - start + 5:
+ - Y'\ :sub:`10[7:0]`
+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]`
+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]`
+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]`
+ - Y'\ :sub:`13[9:2]`
+ * - start + 10:
+ - Y'\ :sub:`20[7:0]`
+ - Y'\ :sub:`21[5:0]`\ Y'\ :sub:`20[9:8]`
+ - Y'\ :sub:`22[3:0]`\ Y'\ :sub:`21[9:6]`
+ - Y'\ :sub:`23[1:0]`\ Y'\ :sub:`22[9:4]`
+ - Y'\ :sub:`23[9:2]`
+ * - start + 15:
+ - Y'\ :sub:`30[7:0]`
+ - Y'\ :sub:`31[5:0]`\ Y'\ :sub:`30[9:8]`
+ - Y'\ :sub:`32[3:0]`\ Y'\ :sub:`31[9:6]`
+ - Y'\ :sub:`33[1:0]`\ Y'\ :sub:`32[9:4]`
+ - Y'\ :sub:`33[9:2]`
+ * - start + 20:
+ - Cb\ :sub:`00[7:0]`
+ - Cr\ :sub:`00[5:0]`\ Cb\ :sub:`00[9:8]`
+ - Cb\ :sub:`01[3:0]`\ Cr\ :sub:`00[9:6]`
+ - Cr\ :sub:`01[1:0]`\ Cb\ :sub:`01[9:4]`
+ - Cr\ :sub:`01[9:2]`
+ * - start + 25:
+ - Cb\ :sub:`10[7:0]`
+ - Cr\ :sub:`10[5:0]`\ Cb\ :sub:`10[9:8]`
+ - Cb\ :sub:`11[3:0]`\ Cr\ :sub:`10[9:6]`
+ - Cr\ :sub:`11[1:0]`\ Cb\ :sub:`11[9:4]`
+ - Cr\ :sub:`11[9:2]`
+
+
.. _V4L2-PIX-FMT-NV12MT:
.. _V4L2-PIX-FMT-NV12MT-16X16:
.. _V4L2-PIX-FMT-NV12-4L4:
@@ -631,6 +696,69 @@ number of lines as the luma plane.
- Cr\ :sub:`32`
+.. _V4L2-PIX-FMT-NV20:
+
+NV20
+----
+
+Semi-planar 10-bit YUV 4:2:2 format similar to NV16, using 10-bit components
+with no padding between each component. A group of 4 components are stored over
+5 bytes in little endian order.
+
+.. flat-table:: Sample 4x4 NV20 Image (1 byte per cell)
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - Y'\ :sub:`00[7:0]`
+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]`
+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]`
+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]`
+ - Y'\ :sub:`03[9:2]`
+ * - start + 5:
+ - Y'\ :sub:`10[7:0]`
+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]`
+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]`
+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]`
+ - Y'\ :sub:`13[9:2]`
+ * - start + 10:
+ - Y'\ :sub:`20[7:0]`
+ - Y'\ :sub:`21[5:0]`\ Y'\ :sub:`20[9:8]`
+ - Y'\ :sub:`22[3:0]`\ Y'\ :sub:`21[9:6]`
+ - Y'\ :sub:`23[1:0]`\ Y'\ :sub:`22[9:4]`
+ - Y'\ :sub:`23[9:2]`
+ * - start + 15:
+ - Y'\ :sub:`30[7:0]`
+ - Y'\ :sub:`31[5:0]`\ Y'\ :sub:`30[9:8]`
+ - Y'\ :sub:`32[3:0]`\ Y'\ :sub:`31[9:6]`
+ - Y'\ :sub:`33[1:0]`\ Y'\ :sub:`32[9:4]`
+ - Y'\ :sub:`33[9:2]`
+ * - start + 20:
+ - Cb\ :sub:`00[7:0]`
+ - Cr\ :sub:`00[5:0]`\ Cb\ :sub:`00[9:8]`
+ - Cb\ :sub:`01[3:0]`\ Cr\ :sub:`00[9:6]`
+ - Cr\ :sub:`01[1:0]`\ Cb\ :sub:`01[9:4]`
+ - Cr\ :sub:`01[9:2]`
+ * - start + 25:
+ - Cb\ :sub:`10[7:0]`
+ - Cr\ :sub:`10[5:0]`\ Cb\ :sub:`10[9:8]`
+ - Cb\ :sub:`11[3:0]`\ Cr\ :sub:`10[9:6]`
+ - Cr\ :sub:`11[1:0]`\ Cb\ :sub:`11[9:4]`
+ - Cr\ :sub:`11[9:2]`
+ * - start + 30:
+ - Cb\ :sub:`20[7:0]`
+ - Cr\ :sub:`20[5:0]`\ Cb\ :sub:`20[9:8]`
+ - Cb\ :sub:`21[3:0]`\ Cr\ :sub:`20[9:6]`
+ - Cr\ :sub:`21[1:0]`\ Cb\ :sub:`21[9:4]`
+ - Cr\ :sub:`21[9:2]`
+ * - start + 35:
+ - Cb\ :sub:`30[7:0]`
+ - Cr\ :sub:`30[5:0]`\ Cb\ :sub:`30[9:8]`
+ - Cb\ :sub:`31[3:0]`\ Cr\ :sub:`30[9:6]`
+ - Cr\ :sub:`31[1:0]`\ Cb\ :sub:`31[9:4]`
+ - Cr\ :sub:`31[9:2]`
+
+
.. _V4L2-PIX-FMT-NV24:
.. _V4L2-PIX-FMT-NV42:
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index d9b0766f3073f..f685714b05776 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -277,8 +277,10 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
/* YUV planar formats */
{ .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2 },
{ .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2 },
+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 10, 0, 0 }, .bpp_div = { 4, 4, 1, 1 }, .hdiv = 2, .vdiv = 2 },
{ .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 10, 0, 0 }, .bpp_div = { 4, 4, 1, 1 }, .hdiv = 2, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 },
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index a16fb44c7246e..e97881f74c0d7 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1363,8 +1363,10 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_PIX_FMT_YUV48_12: descr = "12-bit YUV 4:4:4 Packed"; break;
case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break;
case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break;
+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break;
case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break;
+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break;
case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break;
case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break;
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index af86ece741e94..ca7b3e8863ca3 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -651,8 +651,10 @@ struct v4l2_pix_format {
/* two planes -- one Y, one Cr + Cb interleaved */
#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */
#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
#define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */
--
2.44.0
From ea1996ad11c92d9d64f8554108a17cb21851e21f Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:02 +0000
Subject: [PATCH 16/34] media: rkvdec: h264: Use bytesperline and buffer height
as virstride
Use bytesperline and buffer height to calculate the strides configured.
This does not really change anything other than ensuring the
bytesperline that is signaled to userspace matches what is configured
in HW.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 4fc167b42cf0c..7a1e76d423df5 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx,
dma_addr_t rlc_addr;
dma_addr_t refer_addr;
u32 rlc_len;
- u32 hor_virstride = 0;
- u32 ver_virstride = 0;
- u32 y_virstride = 0;
+ u32 hor_virstride;
+ u32 ver_virstride;
+ u32 y_virstride;
u32 yuv_virstride = 0;
u32 offset;
dma_addr_t dst_addr;
@@ -909,16 +909,16 @@ static void config_registers(struct rkvdec_ctx *ctx,
f = &ctx->decoded_fmt;
dst_fmt = &f->fmt.pix_mp;
- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8;
- ver_virstride = round_up(dst_fmt->height, 16);
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
+ ver_virstride = dst_fmt->height;
y_virstride = hor_virstride * ver_virstride;
if (sps->chroma_format_idc == 0)
yuv_virstride = y_virstride;
else if (sps->chroma_format_idc == 1)
- yuv_virstride += y_virstride + y_virstride / 2;
+ yuv_virstride = y_virstride + y_virstride / 2;
else if (sps->chroma_format_idc == 2)
- yuv_virstride += 2 * y_virstride;
+ yuv_virstride = 2 * y_virstride;
reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
--
2.44.0
From 02060be800d62fb3b47e080d456ab36797f73445 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 5 Nov 2023 16:55:03 +0000
Subject: [PATCH 17/34] media: rkvdec: h264: Don't hardcode SPS/PPS parameters
Some SPS/PPS parameters are currently hardcoded in the driver even
though they exist in the stable uapi controls.
Use values from SPS/PPS controls instead of hardcoding them.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
[jonas@kwiboo.se: constraint_set_flags condition, commit message]
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 7a1e76d423df5..8bce8902b8dda 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
/* write sps */
- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID);
- WRITE_PPS(0xff, PROFILE_IDC);
- WRITE_PPS(1, CONSTRAINT_SET3_FLAG);
+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(sps->profile_idc, PROFILE_IDC);
+ WRITE_PPS(!!(sps->constraint_set_flags & (1 << 3)), CONSTRAINT_SET3_FLAG);
WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA);
WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA);
- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS),
+ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG);
WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4);
WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES);
WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE);
@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
DIRECT_8X8_INFERENCE_FLAG);
/* write pps */
- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID);
- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
+ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE),
ENTROPY_CODING_MODE_FLAG);
WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT),
--
2.44.0
From 19071eeb798b317e024487b98479b2f9f795bb17 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:04 +0000
Subject: [PATCH 18/34] media: rkvdec: h264: Remove SPS validation at streaming
start
SPS parameters is validated in try_ctrl() ops so there is no need to
re-validate when streaming starts.
Remove the unnecessary call to validate sps at streaming start.
Suggested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 19 ++-----------------
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 8bce8902b8dda..815d5359ddd5c 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -1070,17 +1070,6 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
struct rkvdec_dev *rkvdec = ctx->dev;
struct rkvdec_h264_priv_tbl *priv_tbl;
struct rkvdec_h264_ctx *h264_ctx;
- struct v4l2_ctrl *ctrl;
- int ret;
-
- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
- V4L2_CID_STATELESS_H264_SPS);
- if (!ctrl)
- return -EINVAL;
-
- ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
- if (ret)
- return ret;
h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL);
if (!h264_ctx)
@@ -1089,8 +1078,8 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
&h264_ctx->priv_tbl.dma, GFP_KERNEL);
if (!priv_tbl) {
- ret = -ENOMEM;
- goto err_free_ctx;
+ kfree(h264_ctx);
+ return -ENOMEM;
}
h264_ctx->priv_tbl.size = sizeof(*priv_tbl);
@@ -1100,10 +1089,6 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
ctx->priv = h264_ctx;
return 0;
-
-err_free_ctx:
- kfree(h264_ctx);
- return ret;
}
static void rkvdec_h264_stop(struct rkvdec_ctx *ctx)
--
2.44.0
From fb5850f653c012164fc1d5db8db42b047ea86c51 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:05 +0000
Subject: [PATCH 19/34] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt into
helper
Extract call to v4l2_fill_pixfmt_mp() and ajusting of sizeimage into a
helper. Replace current code with a call to the new helper.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 65befffc35696..4857410a20d0c 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -27,6 +27,16 @@
#include "rkvdec.h"
#include "rkvdec-regs.h"
+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
+ struct v4l2_pix_format_mplane *pix_mp)
+{
+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
+ pix_mp->width, pix_mp->height);
+ pix_mp->plane_fmt[0].sizeimage += 128 *
+ DIV_ROUND_UP(pix_mp->width, 16) *
+ DIV_ROUND_UP(pix_mp->height, 16);
+}
+
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
{
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
@@ -192,13 +202,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
- ctx->coded_fmt_desc->decoded_fmts[0],
- ctx->coded_fmt.fmt.pix_mp.width,
- ctx->coded_fmt.fmt.pix_mp.height);
- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 *
- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) *
- DIV_ROUND_UP(f->fmt.pix_mp.height, 16);
+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
}
static int rkvdec_enum_framesizes(struct file *file, void *priv,
@@ -270,12 +276,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
&pix_mp->height,
&coded_desc->frmsize);
- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
- pix_mp->width, pix_mp->height);
- pix_mp->plane_fmt[0].sizeimage +=
- 128 *
- DIV_ROUND_UP(pix_mp->width, 16) *
- DIV_ROUND_UP(pix_mp->height, 16);
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
pix_mp->field = V4L2_FIELD_NONE;
return 0;
--
2.44.0
From 585bc8cf3fac4a59749d1f564245d5eb9981ebaf Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:06 +0000
Subject: [PATCH 20/34] media: rkvdec: Move rkvdec_reset_decoded_fmt helper
Move rkvdec_reset_decoded_fmt() and the called rkvdec_reset_fmt() helper
functions in preparation for adding a new caller in an upcoming patch.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 46 +++++++++++++--------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 4857410a20d0c..fd5a8a78070ef 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -37,6 +37,29 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
DIV_ROUND_UP(pix_mp->height, 16);
}
+static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f,
+ u32 fourcc)
+{
+ memset(f, 0, sizeof(*f));
+ f->fmt.pix_mp.pixelformat = fourcc;
+ f->fmt.pix_mp.field = V4L2_FIELD_NONE;
+ f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709;
+ f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
+ f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
+}
+
+static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
+{
+ struct v4l2_format *f = &ctx->decoded_fmt;
+
+ rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
+}
+
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
{
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
@@ -169,18 +192,6 @@ rkvdec_find_coded_fmt_desc(u32 fourcc)
return NULL;
}
-static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f,
- u32 fourcc)
-{
- memset(f, 0, sizeof(*f));
- f->fmt.pix_mp.pixelformat = fourcc;
- f->fmt.pix_mp.field = V4L2_FIELD_NONE;
- f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709;
- f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
- f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT;
- f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT;
-}
-
static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
{
struct v4l2_format *f = &ctx->coded_fmt;
@@ -196,17 +207,6 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
ctx->coded_fmt_desc->ops->adjust_fmt(ctx, f);
}
-static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
-{
- struct v4l2_format *f = &ctx->decoded_fmt;
-
- rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
- f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
- f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
- f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
- rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp);
-}
-
static int rkvdec_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
--
2.44.0
From ba07254d5b1c699a9c4f695bff20a602a3fa0d46 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:07 +0000
Subject: [PATCH 21/34] media: rkvdec: Extract decoded format enumeration into
helper
Add a rkvdec_is_valid_fmt() helper that check if a fourcc is a supported
CAPTURE format, and a rkvdec_enum_decoded_fmt() helper that enumerate
valid formats.
This move current code into helper functions in preparation for adding
CAPTURE format filtering and validation in next patch.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 49 +++++++++++++++++++--------
1 file changed, 35 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index fd5a8a78070ef..938a8e3e5c768 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -27,6 +27,32 @@
#include "rkvdec.h"
#include "rkvdec-regs.h"
+static u32 rkvdec_enum_decoded_fmt(struct rkvdec_ctx *ctx, int index)
+{
+ const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+
+ if (WARN_ON(!desc))
+ return 0;
+
+ if (index >= desc->num_decoded_fmts)
+ return 0;
+
+ return desc->decoded_fmts[index];
+}
+
+static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc)
+{
+ const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+ unsigned int i;
+
+ for (i = 0; i < desc->num_decoded_fmts; i++) {
+ if (desc->decoded_fmts[i] == fourcc)
+ return true;
+ }
+
+ return false;
+}
+
static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
struct v4l2_pix_format_mplane *pix_mp)
{
@@ -52,8 +78,10 @@ static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f,
static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
{
struct v4l2_format *f = &ctx->decoded_fmt;
+ u32 fourcc;
- rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ fourcc = rkvdec_enum_decoded_fmt(ctx, 0);
+ rkvdec_reset_fmt(ctx, f, fourcc);
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height;
@@ -250,7 +278,6 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
const struct rkvdec_coded_fmt_desc *coded_desc;
- unsigned int i;
/*
* The codec context should point to a coded format desc, if the format
@@ -261,13 +288,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
if (WARN_ON(!coded_desc))
return -EINVAL;
- for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
- break;
- }
-
- if (i == coded_desc->num_decoded_fmts)
- pix_mp->pixelformat = coded_desc->decoded_fmts[0];
+ if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat))
+ pix_mp->pixelformat = rkvdec_enum_decoded_fmt(ctx, 0);
/* Always apply the frmsize constraint of the coded end. */
pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
@@ -431,14 +453,13 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+ u32 fourcc;
- if (WARN_ON(!ctx->coded_fmt_desc))
- return -EINVAL;
-
- if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
+ fourcc = rkvdec_enum_decoded_fmt(ctx, f->index);
+ if (!fourcc)
return -EINVAL;
- f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index];
+ f->pixelformat = fourcc;
return 0;
}
--
2.44.0
From f4d489159d0da96d74b38ef905e86a74e128dae9 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:08 +0000
Subject: [PATCH 22/34] media: rkvdec: Add image format concept
Add an enum rkvdec_image_fmt used to signal an image format, e.g.
4:2:0 8-bit, 4:2:0 10-bit or any.
Tag each supported CAPUTRE format with an image format and use this tag
to filter out unsupported CAPTURE formats.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 45 ++++++++++++++++++++-------
drivers/staging/media/rkvdec/rkvdec.h | 13 +++++++-
2 files changed, 45 insertions(+), 13 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 938a8e3e5c768..6614a9f777d59 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -27,26 +27,42 @@
#include "rkvdec.h"
#include "rkvdec-regs.h"
-static u32 rkvdec_enum_decoded_fmt(struct rkvdec_ctx *ctx, int index)
+static inline bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1,
+ enum rkvdec_image_fmt fmt2)
+{
+ return fmt1 == fmt2 || fmt2 == RKVDEC_IMG_FMT_ANY ||
+ fmt1 == RKVDEC_IMG_FMT_ANY;
+}
+
+static u32 rkvdec_enum_decoded_fmt(struct rkvdec_ctx *ctx, int index,
+ enum rkvdec_image_fmt image_fmt)
{
const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+ unsigned int i, j;
if (WARN_ON(!desc))
return 0;
- if (index >= desc->num_decoded_fmts)
- return 0;
+ for (i = 0, j = 0; i < desc->num_decoded_fmts; i++) {
+ if (rkvdec_image_fmt_match(desc->decoded_fmts[i].image_fmt,
+ image_fmt) &&
+ index == j++)
+ return desc->decoded_fmts[i].fourcc;
+ }
- return desc->decoded_fmts[index];
+ return 0;
}
-static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc)
+static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc,
+ enum rkvdec_image_fmt image_fmt)
{
const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
unsigned int i;
for (i = 0; i < desc->num_decoded_fmts; i++) {
- if (desc->decoded_fmts[i] == fourcc)
+ if (rkvdec_image_fmt_match(desc->decoded_fmts[i].image_fmt,
+ image_fmt) &&
+ desc->decoded_fmts[i].fourcc == fourcc)
return true;
}
@@ -80,7 +96,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
struct v4l2_format *f = &ctx->decoded_fmt;
u32 fourcc;
- fourcc = rkvdec_enum_decoded_fmt(ctx, 0);
+ fourcc = rkvdec_enum_decoded_fmt(ctx, 0, ctx->image_fmt);
rkvdec_reset_fmt(ctx, f, fourcc);
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width;
@@ -149,8 +165,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
};
-static const u32 rkvdec_h264_vp9_decoded_fmts[] = {
- V4L2_PIX_FMT_NV12,
+static const struct rkvdec_decoded_fmt_desc rkvdec_h264_vp9_decoded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT,
+ },
};
static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {
@@ -288,8 +307,9 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
if (WARN_ON(!coded_desc))
return -EINVAL;
- if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat))
- pix_mp->pixelformat = rkvdec_enum_decoded_fmt(ctx, 0);
+ if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat, ctx->image_fmt))
+ pix_mp->pixelformat = rkvdec_enum_decoded_fmt(ctx, 0,
+ ctx->image_fmt);
/* Always apply the frmsize constraint of the coded end. */
pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
@@ -406,6 +426,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
*
* Note that this will propagates any size changes to the decoded format.
*/
+ ctx->image_fmt = RKVDEC_IMG_FMT_ANY;
rkvdec_reset_decoded_fmt(ctx);
/* Propagate colorspace information to capture. */
@@ -455,7 +476,7 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
u32 fourcc;
- fourcc = rkvdec_enum_decoded_fmt(ctx, f->index);
+ fourcc = rkvdec_enum_decoded_fmt(ctx, f->index, ctx->image_fmt);
if (!fourcc)
return -EINVAL;
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 633335ebb9c49..6f8cf50c5d99a 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -75,13 +75,23 @@ struct rkvdec_coded_fmt_ops {
int (*try_ctrl)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
};
+enum rkvdec_image_fmt {
+ RKVDEC_IMG_FMT_ANY = 0,
+ RKVDEC_IMG_FMT_420_8BIT,
+};
+
+struct rkvdec_decoded_fmt_desc {
+ u32 fourcc;
+ enum rkvdec_image_fmt image_fmt;
+};
+
struct rkvdec_coded_fmt_desc {
u32 fourcc;
struct v4l2_frmsize_stepwise frmsize;
const struct rkvdec_ctrls *ctrls;
const struct rkvdec_coded_fmt_ops *ops;
unsigned int num_decoded_fmts;
- const u32 *decoded_fmts;
+ const struct rkvdec_decoded_fmt_desc *decoded_fmts;
u32 subsystem_flags;
};
@@ -104,6 +114,7 @@ struct rkvdec_ctx {
const struct rkvdec_coded_fmt_desc *coded_fmt_desc;
struct v4l2_ctrl_handler ctrl_hdl;
struct rkvdec_dev *dev;
+ enum rkvdec_image_fmt image_fmt;
void *priv;
};
--
2.44.0
From f71dbbd99679405a832878705464e10198993ece Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:09 +0000
Subject: [PATCH 23/34] media: rkvdec: Add get_image_fmt ops
Add support for a get_image_fmt() ops that return the required image
format.
The CAPTURE format is reset when required image format changes and the
buffer queue is not busy.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 49 +++++++++++++++++++++++++--
drivers/staging/media/rkvdec/rkvdec.h | 2 ++
2 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 6614a9f777d59..40daf7eb41ead 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -108,15 +108,60 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
{
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+ struct v4l2_pix_format_mplane *pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
+ enum rkvdec_image_fmt image_fmt;
+ struct vb2_queue *vq;
+ int ret;
+
+ if (desc->ops->try_ctrl) {
+ ret = desc->ops->try_ctrl(ctx, ctrl);
+ if (ret)
+ return ret;
+ }
+
+ if (!desc->ops->get_image_fmt)
+ return 0;
- if (desc->ops->try_ctrl)
- return desc->ops->try_ctrl(ctx, ctrl);
+ image_fmt = desc->ops->get_image_fmt(ctx, ctrl);
+ if (ctx->image_fmt == image_fmt)
+ return 0;
+
+ if (rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat, image_fmt))
+ return 0;
+
+ /* format change not allowed when queue is busy */
+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,
+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ if (vb2_is_busy(vq))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+ const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc;
+ struct v4l2_pix_format_mplane *pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
+ enum rkvdec_image_fmt image_fmt;
+
+ if (!desc->ops->get_image_fmt)
+ return 0;
+
+ image_fmt = desc->ops->get_image_fmt(ctx, ctrl);
+ if (ctx->image_fmt == image_fmt)
+ return 0;
+
+ ctx->image_fmt = image_fmt;
+ if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat, ctx->image_fmt))
+ rkvdec_reset_decoded_fmt(ctx);
return 0;
}
static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
.try_ctrl = rkvdec_try_ctrl,
+ .s_ctrl = rkvdec_s_ctrl,
};
static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 6f8cf50c5d99a..e466a2753ccfc 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -73,6 +73,8 @@ struct rkvdec_coded_fmt_ops {
struct vb2_v4l2_buffer *dst_buf,
enum vb2_buffer_state result);
int (*try_ctrl)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl);
+ enum rkvdec_image_fmt (*get_image_fmt)(struct rkvdec_ctx *ctx,
+ struct v4l2_ctrl *ctrl);
};
enum rkvdec_image_fmt {
--
2.44.0
From 38bde1b170d3362f845f3a985bc4c2ed88f510fe Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 16:55:10 +0000
Subject: [PATCH 24/34] media: rkvdec: h264: Support High 10 and 4:2:2 profiles
Add support and enable decoding of H264 High 10 and 4:2:2 profiles.
Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW
requirement of 10-bit format buffers, fixes decoding of:
- Hi422FR13_SONY_A
- Hi422FR14_SONY_A
- Hi422FR15_SONY_A
- Hi422FR6_SONY_A
- Hi422FR7_SONY_A
- Hi422FR8_SONY_A
- Hi422FR9_SONY_A
- Hi422FREXT18_SONY_A
The get_image_fmt() ops is implemented to select an image format
required for the provided SPS control.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 37 ++++++++++++++++------
drivers/staging/media/rkvdec/rkvdec.c | 33 +++++++++++++++----
drivers/staging/media/rkvdec/rkvdec.h | 3 ++
3 files changed, 57 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 815d5359ddd5c..baac6d012dddf 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -1027,24 +1027,42 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
return 0;
}
+static enum rkvdec_image_fmt rkvdec_h264_get_image_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
+
+ if (ctrl->id != V4L2_CID_STATELESS_H264_SPS)
+ return RKVDEC_IMG_FMT_ANY;
+
+ if (sps->bit_depth_luma_minus8 == 0) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_8BIT;
+ else
+ return RKVDEC_IMG_FMT_420_8BIT;
+ } else if (sps->bit_depth_luma_minus8 == 2) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_10BIT;
+ else
+ return RKVDEC_IMG_FMT_420_10BIT;
+ }
+
+ return RKVDEC_IMG_FMT_ANY;
+}
+
static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
const struct v4l2_ctrl_h264_sps *sps)
{
unsigned int width, height;
- /*
- * TODO: The hardware supports 10-bit and 4:2:2 profiles,
- * but it's currently broken in the driver.
- * Reject them for now, until it's fixed.
- */
- if (sps->chroma_format_idc > 1)
- /* Only 4:0:0 and 4:2:0 are supported */
+ if (sps->chroma_format_idc > 2)
+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */
return -EINVAL;
if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
/* Luma and chroma bit depth mismatch */
return -EINVAL;
- if (sps->bit_depth_luma_minus8 != 0)
- /* Only 8-bit is supported */
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
+ /* Only 8-bit and 10-bit is supported */
return -EINVAL;
width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
@@ -1175,4 +1193,5 @@ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
.stop = rkvdec_h264_stop,
.run = rkvdec_h264_run,
.try_ctrl = rkvdec_h264_try_ctrl,
+ .get_image_fmt = rkvdec_h264_get_image_fmt,
};
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 40daf7eb41ead..683e43c699231 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -73,7 +73,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx,
struct v4l2_pix_format_mplane *pix_mp)
{
v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat,
- pix_mp->width, pix_mp->height);
+ ALIGN(pix_mp->width, 64), pix_mp->height);
pix_mp->plane_fmt[0].sizeimage += 128 *
DIV_ROUND_UP(pix_mp->width, 16) *
DIV_ROUND_UP(pix_mp->height, 16);
@@ -193,7 +193,7 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
{
.cfg.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
.cfg.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
- .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
+ .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422,
.cfg.menu_skip_mask =
BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
.cfg.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
@@ -210,11 +210,23 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
};
-static const struct rkvdec_decoded_fmt_desc rkvdec_h264_vp9_decoded_fmts[] = {
+static const struct rkvdec_decoded_fmt_desc rkvdec_h264_decoded_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_NV12,
.image_fmt = RKVDEC_IMG_FMT_420_8BIT,
},
+ {
+ .fourcc = V4L2_PIX_FMT_NV15,
+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV16,
+ .image_fmt = RKVDEC_IMG_FMT_422_8BIT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV20,
+ .image_fmt = RKVDEC_IMG_FMT_422_10BIT,
+ },
};
static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = {
@@ -237,6 +249,13 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = {
.num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs),
};
+static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT,
+ },
+};
+
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
@@ -250,8 +269,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
},
.ctrls = &rkvdec_h264_ctrls,
.ops = &rkvdec_h264_fmt_ops,
- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
+ .decoded_fmts = rkvdec_h264_decoded_fmts,
.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
},
{
@@ -266,8 +285,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
},
.ctrls = &rkvdec_vp9_ctrls,
.ops = &rkvdec_vp9_fmt_ops,
- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts),
- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
+ .decoded_fmts = rkvdec_vp9_decoded_fmts,
}
};
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index e466a2753ccfc..9a9f4fced7a18 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -80,6 +80,9 @@ struct rkvdec_coded_fmt_ops {
enum rkvdec_image_fmt {
RKVDEC_IMG_FMT_ANY = 0,
RKVDEC_IMG_FMT_420_8BIT,
+ RKVDEC_IMG_FMT_420_10BIT,
+ RKVDEC_IMG_FMT_422_8BIT,
+ RKVDEC_IMG_FMT_422_10BIT,
};
struct rkvdec_decoded_fmt_desc {
--
2.44.0
From 87acb059d8a1eca6d2612aea773522abe5033332 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 23:36:08 +0000
Subject: [PATCH 25/34] media: rkvdec: Add HEVC backend
The Rockchip VDEC supports the HEVC codec with the Main and Main10
Profile up to Level 5.1 High tier: 4096x2304@60 fps.
Add the backend for HEVC format to the decoder.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/Makefile | 2 +-
drivers/staging/media/rkvdec/TODO | 7 -
.../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-hevc.c | 814 ++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
drivers/staging/media/rkvdec/rkvdec.c | 76 +
drivers/staging/media/rkvdec/rkvdec.h | 1 +
7 files changed, 2741 insertions(+), 8 deletions(-)
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
index cb86b429cfaac..a77122641d141 100644
--- a/drivers/staging/media/rkvdec/Makefile
+++ b/drivers/staging/media/rkvdec/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO
index 2c0779383276e..f089ef859e8c5 100644
--- a/drivers/staging/media/rkvdec/TODO
+++ b/drivers/staging/media/rkvdec/TODO
@@ -1,10 +1,3 @@
-* Support for HEVC is planned for this driver.
-
- Given the V4L controls for that CODEC will be part of
- the uABI, it will be required to have the driver in staging.
-
- For this reason, we are keeping this driver in staging for now.
-
* Evaluate introducing a helper to consolidate duplicated
code in rkvdec_request_validate and cedrus_request_validate.
The helper needs to the driver private data associated with
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
new file mode 100644
index 0000000000000..eac4ea604949f
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
@@ -0,0 +1,1848 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder driver
+ *
+ * Copyright (C) 2023 Collabora, Ltd.
+ * Sebastian Fricke <sebastian.fricke@collabora.com>
+ */
+
+#include <linux/types.h>
+
+#define RKV_CABAC_TABLE_SIZE 27456
+
+/*
+ * This file is #include from rkvdec-hevc.c and not compiled.
+ */
+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f,
+ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40,
+ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60,
+ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50,
+ 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68,
+ 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60,
+ 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58,
+ 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07,
+ 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40,
+ 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37,
+ 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x47, 0x57,
+ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, 0x47, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, 0x57, 0x5e,
+ 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, 0x4f,
+ 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47,
+ 0x66, 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47,
+ 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37,
+ 0x07, 0x57, 0x4f, 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10,
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+ 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f,
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+ 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37,
+ 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
new file mode 100644
index 0000000000000..0c4ddc073a6c8
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder HEVC backend
+ *
+ * Copyright (C) 2023 Collabora, Ltd.
+ * Sebastian Fricke <sebastian.fricke@collabora.com>
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Boris Brezillon <boris.brezillon@collabora.com>
+ *
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
+ * Jeffy Chen <jeffy.chen@rock-chips.com>
+ */
+
+#include <media/v4l2-mem2mem.h>
+
+#include "rkvdec.h"
+#include "rkvdec-regs.h"
+#include "rkvdec-hevc-data.c"
+
+/* Size in u8/u32 units. */
+#define RKV_SCALING_LIST_SIZE 1360
+#define RKV_PPS_SIZE (80 / 4)
+#define RKV_PPS_LEN 64
+#define RKV_RPS_SIZE (32 / 4)
+#define RKV_RPS_LEN 600
+
+struct rkvdec_sps_pps_packet {
+ u32 info[RKV_PPS_SIZE];
+};
+
+struct rkvdec_rps_packet {
+ u32 info[RKV_RPS_SIZE];
+};
+
+struct rkvdec_ps_field {
+ u16 offset;
+ u8 len;
+};
+
+#define PS_FIELD(_offset, _len) \
+ ((struct rkvdec_ps_field){ _offset, _len })
+
+/* SPS */
+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)
+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
+#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
+#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
+#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
+/* PPS */
+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
+#define INIT_QP_MINUS26 PS_FIELD(163, 7)
+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
+#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
+#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
+#define NUM_TILE_ROWS PS_FIELD(217, 5)
+#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8)
+#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8)
+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
+
+/* Data structure describing auxiliary buffer format. */
+struct rkvdec_hevc_priv_tbl {
+ u8 cabac_table[RKV_CABAC_TABLE_SIZE];
+ u8 scaling_list[RKV_SCALING_LIST_SIZE];
+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
+ struct rkvdec_rps_packet rps[RKV_RPS_LEN];
+};
+
+struct rkvdec_hevc_run {
+ struct rkvdec_run base;
+ const struct v4l2_ctrl_hevc_slice_params *slices_params;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps;
+ const struct v4l2_ctrl_hevc_pps *pps;
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
+ int num_slices;
+};
+
+struct rkvdec_hevc_ctx {
+ struct rkvdec_aux_buf priv_tbl;
+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
+};
+
+struct scaling_factor {
+ u8 scalingfactor0[1248];
+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/
+ u8 reserved[4]; /*16Bytes align*/
+};
+
+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
+{
+ u8 bit = field.offset % 32, word = field.offset / 32;
+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
+ u64 val = ((u64)value << bit) & mask;
+
+ buf[word] &= ~mask;
+ buf[word] |= val;
+ if (bit + field.len > 32) {
+ buf[word + 1] &= ~(mask >> 32);
+ buf[word + 1] |= val >> 32;
+ }
+}
+
+static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_pps *pps = run->pps;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_sps_pps_packet *hw_ps;
+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
+ u32 log2_min_cu_qp_delta_size, scaling_distance;
+ dma_addr_t scaling_list_address;
+ int i;
+
+ /*
+ * HW read the SPS/PPS information from PPS packet index by PPS id.
+ * offset from the base can be calculated by PPS_id * 80 (size per PPS
+ * packet unit). so the driver copy SPS/PPS information to the exact PPS
+ * packet unit for HW accessing.
+ */
+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
+ /* write sps */
+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
+ LOG2_MAX_PIC_ORDER_CNT_LSB);
+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
+ LOG2_MIN_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
+ SCALING_LIST_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
+ AMP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
+ WRITE_PPS(1, PCM_ENABLED_FLAG);
+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_CHROMA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
+ PCM_LOOP_FILTER_DISABLED_FLAG);
+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ }
+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
+ LONG_TERM_REF_PICS_PRESENT_FLAG);
+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
+ SPS_TEMPORAL_MVP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
+
+ /* write pps */
+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
+ OUTPUT_FLAG_PRESENT_FLAG);
+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
+ SIGN_DATA_HIDING_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
+ CABAC_INIT_PRESENT_FLAG);
+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
+ NUM_REF_IDX_L0_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
+ NUM_REF_IDX_L1_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
+ CONSTRAINED_INTRA_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
+ TRANSFORM_SKIP_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
+ CU_QP_DELTA_ENABLED_FLAG);
+
+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
+ ctb_log2_size_y = min_cb_log2_size_y +
+ sps->log2_diff_max_min_luma_coding_block_size;
+ ctb_size_y = 1 << ctb_log2_size_y;
+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
+ WEIGHTED_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
+ WEIGHTED_BIPRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
+ TRANSQUANT_BYPASS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
+ TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
+ ENTROPY_CODING_SYNC_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
+ LISTS_MODIFICATION_PRESENT_FLAG);
+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
+
+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
+ /* Userspace also provide column width and row height for uniform spacing */
+ for (i = 0; i <= pps->num_tile_columns_minus1; i++)
+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
+ for (i = 0; i <= pps->num_tile_rows_minus1; i++)
+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
+ } else {
+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
+ COLUMN_WIDTH(0));
+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
+ ROW_HEIGHT(0));
+ }
+
+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
+}
+
+/*
+ * Creation of the Reference Picture Set memory blob for the hardware.
+ * The layout looks like this:
+ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference)
+ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references
+ * + 4 bits of the 13th reference)
+ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and
+ * 21 bits for L1 (4 references + first bit of 5)
+ * [3] 32 bits of padding with 0s
+ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11)
+ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references)
+ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32)
+ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12)
+ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s
+ * [7] 32 bits of padding with 0s
+ *
+ * Thus we have to set up padding in between reference 5 of the L1 list.
+ */
+static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params;
+ const struct v4l2_hevc_dpb_entry *dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_rps_packet *hw_ps;
+ int i, j;
+ unsigned int lowdelay;
+
+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
+
+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1)
+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4)
+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1)
+#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4)
+
+#define LOWDELAY PS_FIELD(182, 1)
+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10)
+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9)
+#define NUM_RPS_POC PS_FIELD(202, 4)
+
+ for (j = 0; j < run->num_slices; j++) {
+ uint st_bit_offset = 0;
+ uint num_l0_refs = 0;
+ uint num_l1_refs = 0;
+
+ sl_params = &run->slices_params[j];
+ dpb = decode_params->dpb;
+
+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
+
+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
+
+ lowdelay = 1;
+ } else {
+ lowdelay = 0;
+ }
+
+ hw_ps = &priv_tbl->rps[j];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ for (i = 0; i < num_l0_refs; i++) {
+ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]];
+
+ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ REF_PIC_LONG_TERM_L0(i));
+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
+
+ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+ }
+
+ for (i = 0; i < num_l1_refs; i++) {
+ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]];
+ int is_long_term =
+ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE);
+
+ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i));
+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
+
+ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+ }
+
+ WRITE_RPS(lowdelay, LOWDELAY);
+
+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
+ if (sl_params->short_term_ref_pic_set_size)
+ st_bit_offset = sl_params->short_term_ref_pic_set_size;
+ else if (sps->num_short_term_ref_pic_sets > 1)
+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
+ }
+
+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
+ LONG_TERM_RPS_BIT_OFFSET);
+ WRITE_RPS(sl_params->short_term_ref_pic_set_size,
+ SHORT_TERM_RPS_BIT_OFFSET);
+
+ WRITE_RPS(decode_params->num_poc_st_curr_before +
+ decode_params->num_poc_st_curr_after +
+ decode_params->num_poc_lt_curr,
+ NUM_RPS_POC);
+ }
+}
+
+/*
+ * Flip one or more matrices along their main diagonal and flatten them
+ * before writing it to the memory.
+ * Convert:
+ * ABCD AEIM
+ * EFGH => BFJN => AEIMBFJNCGKODHLP
+ * IJKL CGKO
+ * MNOP DHLP
+ */
+static void transpose_and_flatten_matrices(u8 *output, const u8 *input,
+ int matrices, int row_length)
+{
+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
+
+ matrix_size = row_length * row_length;
+ for (i = 0; i < matrices; i++) {
+ row = 0;
+ x_offset = 0;
+ matrix_offset = i * matrix_size;
+ for (j = 0; j < matrix_size; j++) {
+ y_offset = j - (row * row_length);
+ rot_index = y_offset * row_length + x_offset;
+ new_value = *(input + i * matrix_size + j);
+ output[matrix_offset + rot_index] = *(input + i * matrix_size + j);
+ if ((j + 1) % row_length == 0) {
+ row += 1;
+ x_offset += 1;
+ }
+ }
+ }
+}
+
+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ int offset = 0;
+
+ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4);
+ offset = 6 * 16 * sizeof(u8);
+ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8);
+ offset += 6 * 64 * sizeof(u8);
+ transpose_and_flatten_matrices(output + offset,
+ (const u8 *)input->scaling_list_16x16, 6, 8);
+ offset += 6 * 64 * sizeof(u8);
+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */
+ transpose_and_flatten_matrices(output + offset,
+ (const u8 *)input->scaling_list_32x32, 1, 8);
+ offset += 64 * sizeof(u8);
+ memset(output + offset, 0, 128);
+ offset += 128 * sizeof(u8);
+ transpose_and_flatten_matrices(output + offset,
+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)),
+ 1, 8);
+ offset += 64 * sizeof(u8);
+ memset(output + offset, 0, 128);
+}
+
+/*
+ * Required layout:
+ * A = scaling_list_dc_coef_16x16
+ * B = scaling_list_dc_coef_32x32
+ * 0 = Padding
+ *
+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0
+ */
+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ u8 list_32x32[6] = {0};
+
+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8));
+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0];
+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1];
+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8));
+}
+
+static void translate_scaling_list(struct scaling_factor *output,
+ const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ assemble_scalingfactor0(output->scalingfactor0, input);
+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96);
+ assemble_scalingdc(output->scalingdc, input);
+ memset(output->reserved, 0, 4 * sizeof(u8));
+}
+
+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
+ u8 *dst;
+
+ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
+ return;
+
+ dst = tbl->scaling_list;
+ translate_scaling_list((struct scaling_factor *)dst, scaling);
+
+ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
+}
+
+static struct vb2_buffer *
+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
+ unsigned int dpb_idx)
+{
+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
+ struct vb2_buffer *buf = NULL;
+
+ if (dpb_idx < decode_params->num_active_dpb_entries)
+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
+
+ /*
+ * If a DPB entry is unused or invalid, the address of current destination
+ * buffer is returned.
+ */
+ if (!buf)
+ return &run->base.bufs.dst->vb2_buf;
+
+ return buf;
+}
+
+static void config_registers(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
+ const struct v4l2_pix_format_mplane *dst_fmt;
+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
+ const struct v4l2_format *f;
+ dma_addr_t rlc_addr;
+ dma_addr_t refer_addr;
+ u32 rlc_len;
+ u32 hor_virstride;
+ u32 ver_virstride;
+ u32 y_virstride;
+ u32 yuv_virstride = 0;
+ u32 offset;
+ dma_addr_t dst_addr;
+ u32 reg, i;
+
+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
+
+ f = &ctx->decoded_fmt;
+ dst_fmt = &f->fmt.pix_mp;
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
+ ver_virstride = dst_fmt->height;
+ y_virstride = hor_virstride * ver_virstride;
+
+ if (sps->chroma_format_idc == 0)
+ yuv_virstride = y_virstride;
+ else if (sps->chroma_format_idc == 1)
+ yuv_virstride = y_virstride + y_virstride / 2;
+ else if (sps->chroma_format_idc == 2)
+ yuv_virstride = 2 * y_virstride;
+
+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
+
+ /* config rlc base address */
+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
+
+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
+
+ /* config cabac table */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
+
+ /* config output base address */
+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
+
+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
+
+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
+
+ /* config ref pic address */
+ for (i = 0; i < 15; i++) {
+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
+
+ if (i < 4 && decode_params->num_active_dpb_entries) {
+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
+ reg = (reg >> (i * 4)) & 0xf;
+ } else {
+ reg = 0;
+ }
+
+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
+ writel_relaxed(refer_addr | reg,
+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
+
+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ?
+ dpb[i].pic_order_cnt_val : 0);
+ writel_relaxed(reg,
+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
+ }
+
+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
+
+ /* config hw pps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_PPS_BASE);
+
+ /* config hw rps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_RPS_BASE);
+
+ reg = RKVDEC_AXI_DDR_RDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
+
+ reg = RKVDEC_AXI_DDR_WDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
+}
+
+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2
+
+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_format *f)
+{
+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
+
+ fmt->num_planes = 1;
+ if (!fmt->plane_fmt[0].sizeimage)
+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
+ return 0;
+}
+
+static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
+
+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS)
+ return RKVDEC_IMG_FMT_ANY;
+
+ if (sps->bit_depth_luma_minus8 == 0) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_8BIT;
+ else
+ return RKVDEC_IMG_FMT_420_8BIT;
+ } else if (sps->bit_depth_luma_minus8 == 2) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_10BIT;
+ else
+ return RKVDEC_IMG_FMT_420_10BIT;
+ }
+
+ return RKVDEC_IMG_FMT_ANY;
+}
+
+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
+ const struct v4l2_ctrl_hevc_sps *sps)
+{
+ if (sps->chroma_format_idc > 1)
+ /* Only 4:0:0 and 4:2:0 are supported */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
+ /* Luma and chroma bit depth mismatch */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
+ /* Only 8-bit and 10-bit is supported */
+ return -EINVAL;
+
+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_priv_tbl *priv_tbl;
+ struct rkvdec_hevc_ctx *hevc_ctx;
+
+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
+ if (!hevc_ctx)
+ return -ENOMEM;
+
+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
+ if (!priv_tbl) {
+ kfree(hevc_ctx);
+ return -ENOMEM;
+ }
+
+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
+ hevc_ctx->priv_tbl.cpu = priv_tbl;
+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
+ sizeof(rkvdec_hevc_cabac_table));
+
+ ctx->priv = hevc_ctx;
+ return 0;
+}
+
+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_dev *rkvdec = ctx->dev;
+
+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
+ kfree(hevc_ctx);
+}
+
+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct v4l2_ctrl *ctrl;
+
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
+ run->num_slices = ctrl->new_elems;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SPS);
+ run->sps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_PPS);
+ run->pps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
+
+ rkvdec_run_preamble(ctx, &run->base);
+}
+
+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_run run;
+
+ rkvdec_hevc_run_preamble(ctx, &run);
+
+ assemble_hw_scaling_list(ctx, &run);
+ assemble_hw_pps(ctx, &run);
+ assemble_hw_rps(ctx, &run);
+ config_registers(ctx, &run);
+
+ rkvdec_run_postamble(ctx, &run.base);
+
+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
+
+ writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+ writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+
+ /* Start decoding! */
+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
+
+ return 0;
+}
+
+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
+
+ return 0;
+}
+
+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
+ .adjust_fmt = rkvdec_hevc_adjust_fmt,
+ .start = rkvdec_hevc_start,
+ .stop = rkvdec_hevc_stop,
+ .run = rkvdec_hevc_run,
+ .try_ctrl = rkvdec_hevc_try_ctrl,
+ .get_image_fmt = rkvdec_hevc_get_image_fmt,
+};
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 15b9bee92016c..83bf790ed9b7d 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -43,6 +43,7 @@
#define RKVDEC_RLC_MODE BIT(11)
#define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
#define RKVDEC_MODE(x) (((x) & 0x03) << 20)
+#define RKVDEC_MODE_HEVC 0
#define RKVDEC_MODE_H264 1
#define RKVDEC_MODE_VP9 2
#define RKVDEC_RPS_MODE BIT(24)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 683e43c699231..1be37d31c2a64 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -164,6 +164,67 @@ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
.s_ctrl = rkvdec_s_ctrl,
};
+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
+ .cfg.dims = { 600 },
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
+ },
+};
+
+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
+ .ctrls = rkvdec_hevc_ctrl_descs,
+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
+};
+
+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV15,
+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT,
+ },
+};
+
static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
{
.cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
@@ -257,6 +318,21 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = {
};
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 4096,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 2304,
+ .step_height = 16,
+ },
+ .ctrls = &rkvdec_hevc_ctrls,
+ .ops = &rkvdec_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ },
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
.frmsize = {
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 9a9f4fced7a18..2f3bda1df5f07 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -138,6 +138,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
#endif /* RKVDEC_H_ */
--
2.44.0
From 173dfc847d97b92efb58ce9fcff6b943166a399a Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 5 Nov 2023 23:36:09 +0000
Subject: [PATCH 26/34] media: rkvdec: Add variants support
Different versions of the Rockchip VDEC IP exists and one way they can
differ is what decoding formats are supported.
Add a variant implementation in order to support flagging different
capabilities.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 21 ++++++++++++++++++++-
drivers/staging/media/rkvdec/rkvdec.h | 10 ++++++++++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 1be37d31c2a64..d9762471a9cde 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -13,6 +13,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
@@ -332,6 +333,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.ops = &rkvdec_hevc_fmt_ops,
.num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
.decoded_fmts = rkvdec_hevc_decoded_fmts,
+ .capability = RKVDEC_CAPABILITY_HEVC,
},
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
@@ -348,6 +350,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts),
.decoded_fmts = rkvdec_h264_decoded_fmts,
.subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF,
+ .capability = RKVDEC_CAPABILITY_H264,
},
{
.fourcc = V4L2_PIX_FMT_VP9_FRAME,
@@ -363,6 +366,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
.ops = &rkvdec_vp9_fmt_ops,
.num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts),
.decoded_fmts = rkvdec_vp9_decoded_fmts,
+ .capability = RKVDEC_CAPABILITY_VP9,
}
};
@@ -1174,8 +1178,17 @@ static void rkvdec_watchdog_func(struct work_struct *work)
}
}
+static const struct rkvdec_variant rk3399_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC |
+ RKVDEC_CAPABILITY_H264 |
+ RKVDEC_CAPABILITY_VP9,
+};
+
static const struct of_device_id of_rkvdec_match[] = {
- { .compatible = "rockchip,rk3399-vdec" },
+ {
+ .compatible = "rockchip,rk3399-vdec",
+ .data = &rk3399_rkvdec_variant,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_rkvdec_match);
@@ -1186,16 +1199,22 @@ static const char * const rkvdec_clk_names[] = {
static int rkvdec_probe(struct platform_device *pdev)
{
+ const struct rkvdec_variant *variant;
struct rkvdec_dev *rkvdec;
unsigned int i;
int ret, irq;
+ variant = of_device_get_match_data(&pdev->dev);
+ if (!variant)
+ return -EINVAL;
+
rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL);
if (!rkvdec)
return -ENOMEM;
platform_set_drvdata(pdev, rkvdec);
rkvdec->dev = &pdev->dev;
+ rkvdec->capabilities = variant->capabilities;
mutex_init(&rkvdec->vdev_lock);
INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func);
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 2f3bda1df5f07..14ce26a6c6186 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -22,6 +22,10 @@
#include <media/videobuf2-core.h>
#include <media/videobuf2-dma-contig.h>
+#define RKVDEC_CAPABILITY_HEVC BIT(0)
+#define RKVDEC_CAPABILITY_H264 BIT(1)
+#define RKVDEC_CAPABILITY_VP9 BIT(2)
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -63,6 +67,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
base.vb.vb2_buf);
}
+struct rkvdec_variant {
+ unsigned int capabilities;
+};
+
struct rkvdec_coded_fmt_ops {
int (*adjust_fmt)(struct rkvdec_ctx *ctx,
struct v4l2_format *f);
@@ -98,6 +106,7 @@ struct rkvdec_coded_fmt_desc {
unsigned int num_decoded_fmts;
const struct rkvdec_decoded_fmt_desc *decoded_fmts;
u32 subsystem_flags;
+ unsigned int capability;
};
struct rkvdec_dev {
@@ -110,6 +119,7 @@ struct rkvdec_dev {
void __iomem *regs;
struct mutex vdev_lock; /* serializes ioctls */
struct delayed_work watchdog_work;
+ unsigned int capabilities;
};
struct rkvdec_ctx {
--
2.44.0
From 298313bae9141cc68f34f393a6cc98bbc3e9179c Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 5 Nov 2023 23:36:11 +0000
Subject: [PATCH 27/34] media: rkvdec: Add RK3288 variant
Add a RK3288 variant, a version of the Rockchip VDEC IP that only
support HEVC decoding.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index d9762471a9cde..ea53625e33344 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1178,6 +1178,10 @@ static void rkvdec_watchdog_func(struct work_struct *work)
}
}
+static const struct rkvdec_variant rk3288_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC,
+};
+
static const struct rkvdec_variant rk3399_rkvdec_variant = {
.capabilities = RKVDEC_CAPABILITY_HEVC |
RKVDEC_CAPABILITY_H264 |
@@ -1185,6 +1189,10 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
};
static const struct of_device_id of_rkvdec_match[] = {
+ {
+ .compatible = "rockchip,rk3288-vdec",
+ .data = &rk3288_rkvdec_variant,
+ },
{
.compatible = "rockchip,rk3399-vdec",
.data = &rk3399_rkvdec_variant,
--
2.44.0
From 78ddad78bbb1816fae06acea0db30bba8637186a Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 5 Nov 2023 23:36:12 +0000
Subject: [PATCH 28/34] media: rkvdec: Disable QoS for HEVC and VP9 on RK3328
The RK3328 VDEC has a HW quirk that require QoS to be disabled when HEVC
or VP9 is decoded, otherwise the decoded picture may become corrupted.
Add a RK3328 variant with a quirk flag to disable QoS when before
decoding is started.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
drivers/staging/media/rkvdec/rkvdec-hevc.c | 9 +++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++
drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 ++++++++++
drivers/staging/media/rkvdec/rkvdec.c | 12 ++++++++++++
drivers/staging/media/rkvdec/rkvdec.h | 4 ++++
5 files changed, 37 insertions(+)
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
index 0c4ddc073a6c8..d0a1859d54c12 100644
--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -788,6 +788,15 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) {
+ u32 reg;
+
+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ reg |= 0xFFFF;
+ reg &= ~BIT(12);
+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ }
+
/* Start decoding! */
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 83bf790ed9b7d..740bdb4986340 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -218,6 +218,8 @@
#define RKVDEC_REG_H264_ERR_E 0x134
#define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff)
+#define RKVDEC_REG_QOS_CTRL 0x18C
+
#define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410
#define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450
diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
index 0e7e16f20eeb0..cadb9d5923089 100644
--- a/drivers/staging/media/rkvdec/rkvdec-vp9.c
+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
@@ -824,6 +824,16 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+
+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) {
+ u32 reg;
+
+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ reg |= 0xFFFF;
+ reg &= ~BIT(12);
+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ }
+
/* Start decoding! */
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index ea53625e33344..41980583527ef 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1182,6 +1182,13 @@ static const struct rkvdec_variant rk3288_rkvdec_variant = {
.capabilities = RKVDEC_CAPABILITY_HEVC,
};
+static const struct rkvdec_variant rk3328_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC |
+ RKVDEC_CAPABILITY_H264 |
+ RKVDEC_CAPABILITY_VP9,
+ .quirks = RKVDEC_QUIRK_DISABLE_QOS,
+};
+
static const struct rkvdec_variant rk3399_rkvdec_variant = {
.capabilities = RKVDEC_CAPABILITY_HEVC |
RKVDEC_CAPABILITY_H264 |
@@ -1193,6 +1200,10 @@ static const struct of_device_id of_rkvdec_match[] = {
.compatible = "rockchip,rk3288-vdec",
.data = &rk3288_rkvdec_variant,
},
+ {
+ .compatible = "rockchip,rk3328-vdec",
+ .data = &rk3328_rkvdec_variant,
+ },
{
.compatible = "rockchip,rk3399-vdec",
.data = &rk3399_rkvdec_variant,
@@ -1223,6 +1234,7 @@ static int rkvdec_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, rkvdec);
rkvdec->dev = &pdev->dev;
rkvdec->capabilities = variant->capabilities;
+ rkvdec->quirks = variant->quirks;
mutex_init(&rkvdec->vdev_lock);
INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func);
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 14ce26a6c6186..1d5d405da56cb 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -26,6 +26,8 @@
#define RKVDEC_CAPABILITY_H264 BIT(1)
#define RKVDEC_CAPABILITY_VP9 BIT(2)
+#define RKVDEC_QUIRK_DISABLE_QOS BIT(0)
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -69,6 +71,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
struct rkvdec_variant {
unsigned int capabilities;
+ unsigned int quirks;
};
struct rkvdec_coded_fmt_ops {
@@ -120,6 +123,7 @@ struct rkvdec_dev {
struct mutex vdev_lock; /* serializes ioctls */
struct delayed_work watchdog_work;
unsigned int capabilities;
+ unsigned int quirks;
};
struct rkvdec_ctx {
--
2.44.0
From 0aa109a3a9b1c670bfea26e2c3072e1195024fc9 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 5 Nov 2023 23:36:13 +0000
Subject: [PATCH 29/34] media: dt-bindings: rockchip,vdec: Add RK3288
compatible
Add a RK3288 compatible for a version of the Rockchip VDEC IP that only
support HEVC decoding.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
index 08b02ec167557..0f00e9c86737a 100644
--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
@@ -16,7 +16,9 @@ description: |-
properties:
compatible:
oneOf:
- - const: rockchip,rk3399-vdec
+ - enum:
+ - rockchip,rk3288-vdec
+ - rockchip,rk3399-vdec
- items:
- enum:
- rockchip,rk3228-vdec
--
2.44.0
From 5b643a8cde73d6063da350cf297889eecc5a88b7 Mon Sep 17 00:00:00 2001
From: Alex Bee <knaerzche@gmail.com>
Date: Sun, 5 Nov 2023 23:36:14 +0000
Subject: [PATCH 30/34] ARM: dts: rockchip: Add vdec node for RK3288
RK3288 contains a Rockchip VDEC block that only support HEVC
decoding. Add a vdec node for this.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index 949bc1829c8fa..dbf2d3b8f13e1 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1296,6 +1296,21 @@
power-domains = <&power RK3288_PD_VIDEO>;
};
+ hevc: video-codec@ff9c0000 {
+ compatible = "rockchip,rk3288-vdec";
+ reg = <0x0 0xff9c0000 0x0 0x440>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+ iommus = <&hevc_mmu>;
+ power-domains = <&power RK3288_PD_HEVC>;
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
@@ -1303,7 +1318,7 @@
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3288_PD_HEVC>;
};
gpu: gpu@ffa30000 {
--
2.44.0
From c03d773d6ac1db294a7a26fc1bc0ad5ae5b46fb3 Mon Sep 17 00:00:00 2001
From: Urja Rannikko <urjaman@gmail.com>
Date: Tue, 28 Sep 2021 20:23:13 +0300
Subject: [PATCH 31/34] Revert "clk: divider: Implement and wire up
.determine_rate by default"
This reverts commit 69a00fb3d6970681c15a23595ec54233ce10295c.
That broke eMMC detection (error -110) on veyron speedy.
Why is still an open question but for now i'm doing this revert
in my tree to be able to test the rest of 5.15 rc's.
---
drivers/clk/clk-divider.c | 23 -----------------------
1 file changed, 23 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c1f426b8a5043..3941b4d984f7d 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -452,27 +452,6 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
divider->width, divider->flags);
}
-static int clk_divider_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- struct clk_divider *divider = to_clk_divider(hw);
-
- /* if read only, just return current value */
- if (divider->flags & CLK_DIVIDER_READ_ONLY) {
- u32 val;
-
- val = clk_div_readl(divider) >> divider->shift;
- val &= clk_div_mask(divider->width);
-
- return divider_ro_determine_rate(hw, req, divider->table,
- divider->width,
- divider->flags, val);
- }
-
- return divider_determine_rate(hw, req, divider->table, divider->width,
- divider->flags);
-}
-
int divider_get_val(unsigned long rate, unsigned long parent_rate,
const struct clk_div_table *table, u8 width,
unsigned long flags)
@@ -528,7 +507,6 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
const struct clk_ops clk_divider_ops = {
.recalc_rate = clk_divider_recalc_rate,
.round_rate = clk_divider_round_rate,
- .determine_rate = clk_divider_determine_rate,
.set_rate = clk_divider_set_rate,
};
EXPORT_SYMBOL_GPL(clk_divider_ops);
@@ -536,7 +514,6 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
const struct clk_ops clk_divider_ro_ops = {
.recalc_rate = clk_divider_recalc_rate,
.round_rate = clk_divider_round_rate,
- .determine_rate = clk_divider_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
--
2.44.0
From c44d82c3bb0f0c035f3d633f23aef2b561ee7f76 Mon Sep 17 00:00:00 2001
From: Sebastian Reichel <sebastian.reichel@collabora.com>
Date: Tue, 30 Jul 2024 20:05:05 +0200
Subject: [PATCH 32/34] mfd: rk8xx: Fix shutdown handler
When I converted rk808 to device managed resources I converted the rk808
specific pm_power_off handler to devm_register_sys_off_handler() using
SYS_OFF_MODE_POWER_OFF_PREPARE, which is allowed to sleep. I did this
because the driver's poweroff function makes use of regmap and the backend
of that might sleep.
But the PMIC poweroff function will kill off the board power and the
kernel does some extra steps after the prepare handler. Thus the prepare
handler should not be used for the PMIC's poweroff routine. Instead the
normal SYS_OFF_MODE_POWER_OFF phase should be used. The old pm_power_off
method is also being called from there, so this would have been a
cleaner conversion anyways.
But it still makes sense to investigate the sleep handling and check
if there are any issues. Apparently the Rockchip and Meson I2C drivers
(the only platforms using the PMICs handled by this driver) both have
support for atomic transfers and thus may be called from the proper
poweroff context.
Things are different on the SPI side. That is so far only used by rk806
and that one is only used by Rockchip RK3588. Unfortunately the Rockchip
SPI driver does not support atomic transfers. That means using the
normal POWER_OFF handler would introduce the following error splash
during shutdown on all RK3588 boards currently supported upstream:
[ 13.761353] ------------[ cut here ]------------
[ 13.761764] Voluntary context switch within RCU read-side critical section!
[ 13.761776] WARNING: CPU: 0 PID: 1 at kernel/rcu/tree_plugin.h:330 rcu_note_context_switch+0x3ac/0x404
[ 13.763219] Modules linked in:
[ 13.763498] CPU: 0 UID: 0 PID: 1 Comm: systemd-shutdow Not tainted 6.10.0-12284-g2818a9a19514 #1499
[ 13.764297] Hardware name: Rockchip RK3588 EVB1 V10 Board (DT)
[ 13.764812] pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 13.765427] pc : rcu_note_context_switch+0x3ac/0x404
[ 13.765871] lr : rcu_note_context_switch+0x3ac/0x404
[ 13.766314] sp : ffff800084f4b5b0
[ 13.766609] x29: ffff800084f4b5b0 x28: ffff00040139b800 x27: 00007dfb4439ae80
[ 13.767245] x26: ffff00040139bc80 x25: 0000000000000000 x24: ffff800082118470
[ 13.767880] x23: 0000000000000000 x22: ffff000400300000 x21: ffff000400300000
[ 13.768515] x20: ffff800083a9d600 x19: ffff0004fee48600 x18: fffffffffffed448
[ 13.769151] x17: 000000040044ffff x16: 005000f2b5503510 x15: 0000000000000048
[ 13.769787] x14: fffffffffffed490 x13: ffff80008473b3c0 x12: 0000000000000900
[ 13.770421] x11: 0000000000000300 x10: ffff800084797bc0 x9 : ffff80008473b3c0
[ 13.771057] x8 : 00000000ffffefff x7 : ffff8000847933c0 x6 : 0000000000000300
[ 13.771692] x5 : 0000000000000301 x4 : 40000000fffff300 x3 : 0000000000000000
[ 13.772328] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000400300000
[ 13.772964] Call trace:
[ 13.773184] rcu_note_context_switch+0x3ac/0x404
[ 13.773598] __schedule+0x94/0xb0c
[ 13.773907] schedule+0x34/0x104
[ 13.774198] schedule_timeout+0x84/0xfc
[ 13.774544] wait_for_completion_timeout+0x78/0x14c
[ 13.774980] spi_transfer_one_message+0x588/0x690
[ 13.775403] __spi_pump_transfer_message+0x19c/0x4ec
[ 13.775846] __spi_sync+0x2a8/0x3c4
[ 13.776161] spi_write_then_read+0x120/0x208
[ 13.776543] rk806_spi_bus_read+0x54/0x88
[ 13.776905] _regmap_raw_read+0xec/0x16c
[ 13.777257] _regmap_bus_read+0x44/0x7c
[ 13.777601] _regmap_read+0x60/0xd8
[ 13.777915] _regmap_update_bits+0xf4/0x13c
[ 13.778289] regmap_update_bits_base+0x64/0x98
[ 13.778686] rk808_power_off+0x70/0xfc
[ 13.779024] sys_off_notify+0x40/0x6c
[ 13.779356] atomic_notifier_call_chain+0x60/0x90
[ 13.779776] do_kernel_power_off+0x54/0x6c
[ 13.780146] machine_power_off+0x18/0x24
[ 13.780499] kernel_power_off+0x70/0x7c
[ 13.780845] __do_sys_reboot+0x210/0x270
[ 13.781198] __arm64_sys_reboot+0x24/0x30
[ 13.781558] invoke_syscall+0x48/0x10c
[ 13.781897] el0_svc_common+0x3c/0xe8
[ 13.782228] do_el0_svc+0x20/0x2c
[ 13.782528] el0_svc+0x34/0xd8
[ 13.782806] el0t_64_sync_handler+0x120/0x12c
[ 13.783197] el0t_64_sync+0x190/0x194
[ 13.783527] ---[ end trace 0000000000000000 ]---
To avoid this we keep the SYS_OFF_MODE_POWER_OFF_PREPARE handler for the
SPI backend. This is not great, but at least avoids regressions and the
fix should be small enough to allow backporting.
As a side-effect this also works around a shutdown problem on the Asus
C201. For reasons unknown that skips calling the prepare handler and
directly calls the final shutdown handler.
Fixes: 4fec8a5a85c49 ("mfd: rk808: Convert to device managed resources")
Cc: stable@vger.kernel.org
Reported-by: Urja <urja@urja.dev>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/mfd/rk8xx-core.c | 16 ++++++++++++++--
drivers/mfd/rk8xx-i2c.c | 2 +-
drivers/mfd/rk8xx-spi.c | 2 +-
include/linux/mfd/rk808.h | 2 +-
4 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c
index 71c2b80a4678d..1583beef714ad 100644
--- a/drivers/mfd/rk8xx-core.c
+++ b/drivers/mfd/rk8xx-core.c
@@ -692,10 +692,11 @@ void rk8xx_shutdown(struct device *dev)
}
EXPORT_SYMBOL_GPL(rk8xx_shutdown);
-int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap)
+int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap, bool is_spi)
{
struct rk808 *rk808;
const struct rk808_reg_data *pre_init_reg;
+ enum sys_off_mode pwr_off_mode = SYS_OFF_MODE_POWER_OFF;
const struct mfd_cell *cells;
int dual_support = 0;
int nr_pre_init_regs;
@@ -785,10 +786,21 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap
if (ret)
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
+ /*
+ * Currently the Rockchip SPI driver always sleeps when doing SPI
+ * transfers. This is not allowed in the SYS_OFF_MODE_POWER_OFF
+ * handler, so we are using the prepare handler as a workaround.
+ * This should be removed once the Rockchip SPI driver has been
+ * adapted.
+ */
+ if (is_spi)
+ pwr_off_mode = SYS_OFF_MODE_POWER_OFF_PREPARE;
+
+
if (device_property_read_bool(dev, "system-power-controller") ||
device_property_read_bool(dev, "rockchip,system-power-controller")) {
ret = devm_register_sys_off_handler(dev,
- SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
+ pwr_off_mode, SYS_OFF_PRIO_HIGH,
&rk808_power_off, rk808);
if (ret)
return dev_err_probe(dev, ret,
diff --git a/drivers/mfd/rk8xx-i2c.c b/drivers/mfd/rk8xx-i2c.c
index 37287b06dab0d..b8c0c368ab8a2 100644
--- a/drivers/mfd/rk8xx-i2c.c
+++ b/drivers/mfd/rk8xx-i2c.c
@@ -213,7 +213,7 @@ static int rk8xx_i2c_probe(struct i2c_client *client)
return dev_err_probe(&client->dev, PTR_ERR(regmap),
"regmap initialization failed\n");
- return rk8xx_probe(&client->dev, data->variant, client->irq, regmap);
+ return rk8xx_probe(&client->dev, data->variant, client->irq, regmap, false);
}
static void rk8xx_i2c_shutdown(struct i2c_client *client)
diff --git a/drivers/mfd/rk8xx-spi.c b/drivers/mfd/rk8xx-spi.c
index 3405fb82ff9fb..20f9428f94bb9 100644
--- a/drivers/mfd/rk8xx-spi.c
+++ b/drivers/mfd/rk8xx-spi.c
@@ -94,7 +94,7 @@ static int rk8xx_spi_probe(struct spi_device *spi)
return dev_err_probe(&spi->dev, PTR_ERR(regmap),
"Failed to init regmap\n");
- return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap);
+ return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap, true);
}
static const struct of_device_id rk8xx_spi_of_match[] = {
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index 69cbea78b430b..be15b84cff9e9 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -1349,7 +1349,7 @@ struct rk808 {
};
void rk8xx_shutdown(struct device *dev);
-int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap);
+int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap, bool is_spi);
int rk8xx_suspend(struct device *dev);
int rk8xx_resume(struct device *dev);
--
2.44.0
From 8721344fc56149fe49c5d233804edd2c380e87ff Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Tue, 20 May 2025 18:10:16 +0100
Subject: [PATCH 33/34] firmware: smccc: Stub out get_conduit()
Various callers use arm_smccc_1_1_get_conduit() to guard their
arm_smccc_smc() calls - since the latter is already stubbed out to
support optional usage in !HAVE_ARM_SMCCC configs, do the equivalent
for the former as well to make life easier.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
include/linux/arm-smccc.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index a3863da1510ee..97dc4d47c6642 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -315,7 +315,14 @@ enum arm_smccc_conduit {
*
* When SMCCCv1.1 is not present, returns SMCCC_CONDUIT_NONE.
*/
+#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void);
+#else
+static inline enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)
+{
+ return SMCCC_CONDUIT_NONE;
+}
+#endif
/**
* arm_smccc_get_version()
--
2.44.0
From ed883f53a9ca7be70904bb965972f52a51fb1930 Mon Sep 17 00:00:00 2001
From: Robin Murphy <robin.murphy@arm.com>
Date: Tue, 20 May 2025 18:10:17 +0100
Subject: [PATCH 34/34] pmdomain: rockchip: Relax SMCCC dependency
Most 32-bit Rockchip platforms do not use PSCI, so having to select
ARM_PSCI to satisfy a dependency chain to retain working power domain
support is a bit weird and non-obvious. Now that the offending SMCCC API
is properly stubbed out for optional usage, we can relax this again.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/pmdomain/rockchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pmdomain/rockchip/Kconfig b/drivers/pmdomain/rockchip/Kconfig
index 218d43186e5b9..ffe5e7b78494f 100644
--- a/drivers/pmdomain/rockchip/Kconfig
+++ b/drivers/pmdomain/rockchip/Kconfig
@@ -4,7 +4,6 @@ if ARCH_ROCKCHIP || COMPILE_TEST
config ROCKCHIP_PM_DOMAINS
bool "Rockchip generic power domain"
depends on PM
- depends on HAVE_ARM_SMCCC_DISCOVERY
depends on REGULATOR
select PM_GENERIC_DOMAINS
help
--
2.44.0