| author | Urja (ARMLFS builder)
<urja+armlfs@urja.dev> 2025-12-23 14:42:42 UTC |
| committer | Urja (ARMLFS builder)
<urja+armlfs@urja.dev> 2025-12-23 14:42:42 UTC |
| parent | d3c5036b9c5bd7d3efa0c237a5a0367ded7a17fa |
| .SRCINFO | +6 | -6 |
| PKGBUILD | +5 | -5 |
| armlfs.patch | +61 | -127 |
diff --git a/.SRCINFO b/.SRCINFO index 053ec59..25bc5ad 100644 --- a/.SRCINFO +++ b/.SRCINFO @@ -1,5 +1,5 @@ pkgbase = linux-armlfs - pkgver = 6.17.7 + pkgver = 6.18.2 pkgrel = 1 url = http://www.kernel.org/ arch = armv7h @@ -28,8 +28,8 @@ pkgbase = linux-armlfs makedepends = sysfsutils makedepends = ncurses options = !strip - source = https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.17.tar.xz - source = https://www.kernel.org/pub/linux/kernel/v6.x/patch-6.17.7.xz + source = https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.18.tar.xz + source = https://www.kernel.org/pub/linux/kernel/v6.x/patch-6.18.2.xz source = armlfs.patch source = kernel.its source = kernel.keyblock @@ -40,9 +40,9 @@ pkgbase = linux-armlfs source = cpupower.service source = usbipd.service source = config - sha256sums = 9b607166a1c999d8326098121222feb080a20a3253975fcdfa2de96ba7f757a7 - sha256sums = a017a72f03a01504f9ba9d9d0882699b451256bf8d4798d8b899fac959e5ff5c - sha256sums = 96805897c4363aedadc1c5e1f3895875f1023f6dbae341f58cb180586e05191b + sha256sums = 9106a4605da9e31ff17659d958782b815f9591ab308d03b0ee21aad6c7dced4b + sha256sums = cc603703572e2efad9d1b59d88def7e7dbed1e807e1e33a17bd08ef26ba7f880 + sha256sums = 06fde4ce84f027894cc98f8032f6836c0b4a5e7559fc083758f34057fd6749dd sha256sums = 994aee74b13313bdc7c47df4d621c890f5ee52bc18f6c7b658de215c17423b2a sha256sums = 4e708c9ec43ac4a5d718474c9431ba6b6da3e64a9dda6afd2853a9e9e3079ffb sha256sums = bc9e707a86e55a93f423e7bcdae4a25fd470b868e53829b91bbe2ccfbc6da27b diff --git a/PKGBUILD b/PKGBUILD index 35e8fd6..afe457a 100644 --- a/PKGBUILD +++ b/PKGBUILD @@ -15,10 +15,10 @@ buildarch=4 _xname= pkgbase=linux-armlfs${_xname} -_srcname=linux-6.17 +_srcname=linux-6.18 _kernelname=${pkgbase#linux} _desc="Veyron Speedy" -pkgver=6.17.7 +pkgver=6.18.2 pkgrel=1 arch=('armv7h') url="http://www.kernel.org/" @@ -333,9 +333,9 @@ package_tmon() { } -sha256sums=('9b607166a1c999d8326098121222feb080a20a3253975fcdfa2de96ba7f757a7' - 'a017a72f03a01504f9ba9d9d0882699b451256bf8d4798d8b899fac959e5ff5c' - '96805897c4363aedadc1c5e1f3895875f1023f6dbae341f58cb180586e05191b' +sha256sums=('9106a4605da9e31ff17659d958782b815f9591ab308d03b0ee21aad6c7dced4b' + 'cc603703572e2efad9d1b59d88def7e7dbed1e807e1e33a17bd08ef26ba7f880' + '06fde4ce84f027894cc98f8032f6836c0b4a5e7559fc083758f34057fd6749dd' '994aee74b13313bdc7c47df4d621c890f5ee52bc18f6c7b658de215c17423b2a' '4e708c9ec43ac4a5d718474c9431ba6b6da3e64a9dda6afd2853a9e9e3079ffb' 'bc9e707a86e55a93f423e7bcdae4a25fd470b868e53829b91bbe2ccfbc6da27b' diff --git a/armlfs.patch b/armlfs.patch index 3753194..3ffeebf 100644 --- a/armlfs.patch +++ b/armlfs.patch @@ -1,7 +1,7 @@ -From 4ab984ed3e35be3ee1ee60bd9c5664e5f0173bc3 Mon Sep 17 00:00:00 2001 +From fed2e3dbaa1cf38e95e50b22ad83b20ebf8a4413 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 10:30:55 +0000 -Subject: [PATCH 01/17] drivers: clk-rk3288: support for dedicating NPLL to a +Subject: [PATCH 01/16] drivers: clk-rk3288: support for dedicating NPLL to a VOP As controlled by the just introduced dts property. @@ -170,10 +170,10 @@ index 7c5e74c7a2e2..76d0a5e093fd 100644 2.44.0 -From 97ad25831d5c589e2705d8537d0698dbb98ecabc Mon Sep 17 00:00:00 2001 +From a53e28e948c0d08f0f3ad6f3882ba66783c7dbf9 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Wed, 22 Aug 2018 18:36:40 +0000 -Subject: [PATCH 02/17] drm: dw_hdmi-rockchip: better clock selection logic and +Subject: [PATCH 02/16] drm: dw_hdmi-rockchip: better clock selection logic and dts-based rate list This contains traces of the following commits from the ChromeOS 3.14 @@ -203,10 +203,10 @@ Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com> 1 file changed, 109 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index acb59b25d928..f029fe4729e7 100644 +index 727cdf768161..ca7283141f0e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -81,8 +81,13 @@ struct rockchip_hdmi { +@@ -80,8 +80,13 @@ struct rockchip_hdmi { struct clk *grf_clk; struct dw_hdmi *hdmi; struct phy *phy; @@ -220,7 +220,7 @@ index acb59b25d928..f029fe4729e7 100644 static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); -@@ -90,6 +95,23 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) +@@ -89,6 +94,23 @@ static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_encoder *encoder) return container_of(rkencoder, struct rockchip_hdmi, encoder); } @@ -244,7 +244,7 @@ index acb59b25d928..f029fe4729e7 100644 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { { 30666000, { -@@ -179,7 +201,7 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { +@@ -178,7 +200,7 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { }; static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { @@ -253,7 +253,7 @@ index acb59b25d928..f029fe4729e7 100644 { 600000000, { 0x0000, 0x0000, 0x0000 }, }, { -@@ -188,18 +210,18 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { +@@ -187,18 +209,18 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { }; static const struct dw_hdmi_phy_config rockchip_phy_config[] = { @@ -278,7 +278,7 @@ index acb59b25d928..f029fe4729e7 100644 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); if (IS_ERR(hdmi->regmap)) { -@@ -227,34 +249,58 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) +@@ -226,34 +248,58 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) return ret; ret = devm_regulator_get_enable(hdmi->dev, "avdd-1v8"); @@ -351,7 +351,7 @@ index acb59b25d928..f029fe4729e7 100644 } return MODE_OK; -@@ -269,7 +315,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, +@@ -268,7 +314,39 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, struct drm_display_mode *adj_mode) { @@ -392,7 +392,7 @@ index acb59b25d928..f029fe4729e7 100644 } static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, -@@ -324,6 +402,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, +@@ -323,6 +401,7 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, } static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { @@ -400,7 +400,7 @@ index acb59b25d928..f029fe4729e7 100644 .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, .mode_set = dw_hdmi_rockchip_encoder_mode_set, .enable = dw_hdmi_rockchip_encoder_enable, -@@ -429,7 +508,9 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { +@@ -423,7 +502,9 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { }; static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { @@ -411,7 +411,7 @@ index acb59b25d928..f029fe4729e7 100644 .phy_data = &rk3228_chip_data, .phy_ops = &rk3228_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", -@@ -444,7 +525,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { +@@ -438,7 +519,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { }; static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { @@ -419,7 +419,7 @@ index acb59b25d928..f029fe4729e7 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -465,7 +545,9 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { +@@ -459,7 +539,9 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { }; static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { @@ -430,7 +430,7 @@ index acb59b25d928..f029fe4729e7 100644 .phy_data = &rk3328_chip_data, .phy_ops = &rk3328_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", -@@ -481,7 +563,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { +@@ -475,7 +557,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { }; static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { @@ -438,7 +438,7 @@ index acb59b25d928..f029fe4729e7 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -495,7 +576,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = { +@@ -489,7 +570,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = { }; static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { @@ -446,7 +446,7 @@ index acb59b25d928..f029fe4729e7 100644 .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, .phy_config = rockchip_phy_config, -@@ -614,6 +694,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -606,6 +686,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return 0; err_bind: @@ -454,7 +454,7 @@ index acb59b25d928..f029fe4729e7 100644 drm_encoder_cleanup(encoder); return ret; -@@ -624,6 +705,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, +@@ -616,6 +697,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); @@ -466,10 +466,10 @@ index acb59b25d928..f029fe4729e7 100644 2.44.0 -From 8641e920d644cc541762983b1ffcc9a9176e2b8b Mon Sep 17 00:00:00 2001 +From 9186a9aa74a293d35f5f46e96b3d0f171c51f75d Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 19:00:50 +0000 -Subject: [PATCH 03/17] dts: rk3288: support for dedicating npll to a vop +Subject: [PATCH 03/16] dts: rk3288: support for dedicating npll to a vop Add the VOP DCLKs to the assigned clocks list so their parents can be set in the dts include files for @@ -505,10 +505,10 @@ index 42d705b544ec..775f24876be4 100644 2.44.0 -From 4ec8a5f3f7fd64e2d63b8260f162c0e723fb6892 Mon Sep 17 00:00:00 2001 +From ce283735f4270f1b4915c41140d101c5160c5bb8 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 19:03:49 +0000 -Subject: [PATCH 04/17] dts: rk3288-veyron-chromebook: dedicate npll to +Subject: [PATCH 04/16] dts: rk3288-veyron-chromebook: dedicate npll to VOP0/HDMI + HDMI rates This enables flexible HDMI rates on the rk3288 chromebooks so that they @@ -598,10 +598,10 @@ index 3677571b4d82..b61a4b0d7015 100644 2.44.0 -From 2e2a23baaffa09c62a4d3fcfe904abd29d6df3ab Mon Sep 17 00:00:00 2001 +From 6cbe99a1dbf651e1c93fcc685c2822a633039ff4 Mon Sep 17 00:00:00 2001 From: SolidHal <hal@halemmerich.com> Date: Sun, 21 Oct 2018 16:40:15 -0500 -Subject: [PATCH 05/17] Added a second reset when having an issue reading the +Subject: [PATCH 05/16] Added a second reset when having an issue reading the emmc. The c201 emmc can be... touchy. Sometimes one full reset isn't @@ -621,10 +621,10 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c -index dd6cffc0df72..04e30d8072da 100644 +index c0ffe0817fd4..7ba50ec3946f 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c -@@ -1090,6 +1090,7 @@ static unsigned int mmc_blk_data_timeout_ms(struct mmc_host *host, +@@ -1052,6 +1052,7 @@ static unsigned int mmc_blk_data_timeout_ms(struct mmc_host *host, static int mmc_blk_reset(struct mmc_blk_data *md, struct mmc_host *host, int type) { @@ -632,7 +632,7 @@ index dd6cffc0df72..04e30d8072da 100644 int err; struct mmc_blk_data *main_md = dev_get_drvdata(&host->card->dev); -@@ -1097,7 +1098,14 @@ static int mmc_blk_reset(struct mmc_blk_data *md, struct mmc_host *host, +@@ -1059,7 +1060,14 @@ static int mmc_blk_reset(struct mmc_blk_data *md, struct mmc_host *host, return -EEXIST; md->reset_done |= type; @@ -651,10 +651,10 @@ index dd6cffc0df72..04e30d8072da 100644 2.44.0 -From 72a28e8fd1a6a9b9c1d037584839e0b69fe3d24b Mon Sep 17 00:00:00 2001 +From a0a4221af5136caa84569206a9473adc43a2f3ae Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Tue, 9 Oct 2018 22:01:07 +0200 -Subject: [PATCH 06/17] block: partitions: efi: Ignore bizarre Chromebook GPT +Subject: [PATCH 06/16] block: partitions: efi: Ignore bizarre Chromebook GPT partitions This patch is based on @SolidHal work here : @@ -804,10 +804,10 @@ index 84b9f36b9e47..09726227e891 100644 2.44.0 -From 3819265762a950222bc849af62073ca8650ed59f Mon Sep 17 00:00:00 2001 +From c30dbce30526f38f7ca96dae8ddcfe1bb0a135fd Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Tue, 30 Oct 2018 22:44:54 +0100 -Subject: [PATCH 07/17] mmc: Added a flag to disable cache flush during reset +Subject: [PATCH 07/16] mmc: Added a flag to disable cache flush during reset The ASUS Chromebook suffer from 10 minutes long hang, when trying to flush the cache of the eMMC, in order to recover from eMMC init @@ -827,10 +827,10 @@ Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr> 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c -index f14671ea5716..c5f8b935f036 100644 +index 88c95dbfd9cf..4640ea5f1db4 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c -@@ -405,6 +405,8 @@ int mmc_of_parse(struct mmc_host *host) +@@ -407,6 +407,8 @@ int mmc_of_parse(struct mmc_host *host) if (device_property_read_bool(dev, "no-mmc-hs400")) host->caps2 &= ~(MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V | MMC_CAP2_HS400_ES); @@ -840,10 +840,10 @@ index f14671ea5716..c5f8b935f036 100644 /* Must be after "non-removable" check */ if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c -index 5be9b42d5057..5e5cfd7c23b3 100644 +index 3e7d9437477c..77f3467f2c71 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c -@@ -2269,6 +2269,12 @@ static int mmc_runtime_resume(struct mmc_host *host) +@@ -2283,6 +2283,12 @@ static int mmc_runtime_resume(struct mmc_host *host) return 0; } @@ -856,7 +856,7 @@ index 5be9b42d5057..5e5cfd7c23b3 100644 static bool mmc_card_can_reset(struct mmc_card *card) { u8 rst_n_function; -@@ -2281,11 +2287,15 @@ static int _mmc_hw_reset(struct mmc_host *host) +@@ -2295,11 +2301,15 @@ static int _mmc_hw_reset(struct mmc_host *host) { struct mmc_card *card = host->card; @@ -877,10 +877,10 @@ index 5be9b42d5057..5e5cfd7c23b3 100644 if ((host->caps & MMC_CAP_HW_RESET) && host->ops->card_hw_reset && mmc_card_can_reset(card)) { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h -index 68f09a955a90..eb7dbf0f9b10 100644 +index e0e2c265e5d1..1d4cd99e5046 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h -@@ -459,6 +459,7 @@ struct mmc_host { +@@ -463,6 +463,7 @@ struct mmc_host { #define MMC_CAP2_CRYPTO 0 #endif #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ @@ -892,10 +892,10 @@ index 68f09a955a90..eb7dbf0f9b10 100644 2.44.0 -From ea5b4995e92d4c8626619f698cb154198bd8f22c Mon Sep 17 00:00:00 2001 +From e01828bcd8f56da008adb124317e0395ce59c849 Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Thu, 1 Nov 2018 21:31:26 +0100 -Subject: [PATCH 08/17] arm: dts: veyron: Added a flag to disable cache flush +Subject: [PATCH 08/16] arm: dts: veyron: Added a flag to disable cache flush during reset Flushing the MMC cache of ASUS Chromebooks during initialization or @@ -925,10 +925,10 @@ index 260d6c92cfd1..08ce8bfb70b2 100644 2.44.0 -From 345c4e8fce7f27d0dc8333da0b794eee792ba5ed Mon Sep 17 00:00:00 2001 +From 31bea3847d9aab9426bd960daa64060fb33eef71 Mon Sep 17 00:00:00 2001 From: Hal Emmerich <hal@halemmerich.com> Date: Wed, 21 Aug 2019 16:52:41 -0500 -Subject: [PATCH 09/17] Fix ath9k dwc2 init frame overruns +Subject: [PATCH 09/16] Fix ath9k dwc2 init frame overruns [ by Urja Rannikko: changed to log message to something more sensible. ] @@ -968,10 +968,10 @@ index 904fe0632b34..6a9ecc809814 100644 2.44.0 -From c21318886beb49dadb692a2d2651c6cd868fa7b6 Mon Sep 17 00:00:00 2001 +From b08489ba76324bc68c72ee89db957fcf05195600 Mon Sep 17 00:00:00 2001 From: barzur <boris@konbu.org> Date: Fri, 12 Jul 2019 11:33:32 +0900 -Subject: [PATCH 10/17] usb/dwc2/hcd: channel halt may not be an error +Subject: [PATCH 10/16] usb/dwc2/hcd: channel halt may not be an error Truncating the data was causing null pointer exceptions in memcpy, let's be more careful. @@ -1039,10 +1039,10 @@ index 5c7538d498dd..96dc5d8115d2 100644 2.44.0 -From 02303386e062c32b99f631ce0aad0eb446267cbb Mon Sep 17 00:00:00 2001 +From 777047f43c55ebb53e1200970595ca23f531bfe9 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 8 Oct 2019 11:03:37 +0000 -Subject: [PATCH 11/17] drm/panel: edp: Extend Innolux N116BGE mode info for +Subject: [PATCH 11/16] drm/panel: edp: Extend Innolux N116BGE mode info for ~60Hz from 74.25 Mhz Signed-off-by: Urja Rannikko <urjaman@gmail.com> @@ -1051,7 +1051,7 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c -index d0aa602ecc9d..2bb437e3afff 100644 +index 62435e3cd9f4..2f83151890ee 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -1294,16 +1294,25 @@ static const struct panel_desc innolux_n116bca_ea1 = { @@ -1086,10 +1086,10 @@ index d0aa602ecc9d..2bb437e3afff 100644 2.44.0 -From f48018ccef2ff63cd129382bd3ff07ecfa1ea649 Mon Sep 17 00:00:00 2001 +From 3d77586cc56eb0ce3653dc6f9fc2b19e8b257a35 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 8 Oct 2019 11:12:33 +0000 -Subject: [PATCH 12/17] ARM: dts: rockchip: Adjust rk3288-veyron n116bge mode +Subject: [PATCH 12/16] ARM: dts: rockchip: Adjust rk3288-veyron n116bge mode for ~60Hz This is an experimental mode that gets very close to 60Hz (60.00067..) @@ -1125,10 +1125,10 @@ index fb031964fa2b..128176b7c372 100644 2.44.0 -From b903c63bb27a2fb905318a4af2e9efb460fee09b Mon Sep 17 00:00:00 2001 +From b34239bb4b784bb3bc2489dded8f79e5d9d5369e Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 25 Dec 2023 18:06:10 +0200 -Subject: [PATCH 13/17] dts: veyron: bluetooth: disable dma on uart0 +Subject: [PATCH 13/16] dts: veyron: bluetooth: disable dma on uart0 I just pulled this off the internet ;) https://codeberg.org/petms/linux-veyron-patches-and-apkbuild @@ -1153,76 +1153,10 @@ index 775f24876be4..a19bf9f83a4d 100644 2.44.0 -From 257adbcb3cdfba3097e204aaf29a5d8f0ff1bd72 Mon Sep 17 00:00:00 2001 -From: Urja Rannikko <urjaman@gmail.com> -Date: Tue, 28 Sep 2021 20:23:13 +0300 -Subject: [PATCH 14/17] Revert "clk: divider: Implement and wire up - .determine_rate by default" - -This reverts commit 69a00fb3d6970681c15a23595ec54233ce10295c. -That broke eMMC detection (error -110) on veyron speedy. -Why is still an open question but for now i'm doing this revert -in my tree to be able to test the rest of 5.15 rc's. ---- - drivers/clk/clk-divider.c | 23 ----------------------- - 1 file changed, 23 deletions(-) - -diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c -index c1f426b8a504..3941b4d984f7 100644 ---- a/drivers/clk/clk-divider.c -+++ b/drivers/clk/clk-divider.c -@@ -452,27 +452,6 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, - divider->width, divider->flags); - } - --static int clk_divider_determine_rate(struct clk_hw *hw, -- struct clk_rate_request *req) --{ -- struct clk_divider *divider = to_clk_divider(hw); -- -- /* if read only, just return current value */ -- if (divider->flags & CLK_DIVIDER_READ_ONLY) { -- u32 val; -- -- val = clk_div_readl(divider) >> divider->shift; -- val &= clk_div_mask(divider->width); -- -- return divider_ro_determine_rate(hw, req, divider->table, -- divider->width, -- divider->flags, val); -- } -- -- return divider_determine_rate(hw, req, divider->table, divider->width, -- divider->flags); --} -- - int divider_get_val(unsigned long rate, unsigned long parent_rate, - const struct clk_div_table *table, u8 width, - unsigned long flags) -@@ -528,7 +507,6 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, - const struct clk_ops clk_divider_ops = { - .recalc_rate = clk_divider_recalc_rate, - .round_rate = clk_divider_round_rate, -- .determine_rate = clk_divider_determine_rate, - .set_rate = clk_divider_set_rate, - }; - EXPORT_SYMBOL_GPL(clk_divider_ops); -@@ -536,7 +514,6 @@ EXPORT_SYMBOL_GPL(clk_divider_ops); - const struct clk_ops clk_divider_ro_ops = { - .recalc_rate = clk_divider_recalc_rate, - .round_rate = clk_divider_round_rate, -- .determine_rate = clk_divider_determine_rate, - }; - EXPORT_SYMBOL_GPL(clk_divider_ro_ops); - --- -2.44.0 - - -From 8d569ab4a97cfbe68f6fbcf87df7631ee8426ec9 Mon Sep 17 00:00:00 2001 +From 111fff833013ce51a622ecd0008f3f458da9f16d Mon Sep 17 00:00:00 2001 From: Sebastian Reichel <sebastian.reichel@collabora.com> Date: Tue, 30 Jul 2024 20:05:05 +0200 -Subject: [PATCH 15/17] mfd: rk8xx: Fix shutdown handler +Subject: [PATCH 14/16] mfd: rk8xx: Fix shutdown handler When I converted rk808 to device managed resources I converted the rk808 specific pm_power_off handler to devm_register_sys_off_handler() using @@ -1403,10 +1337,10 @@ index 28170ee08898..f4ce5968e91c 100644 2.44.0 -From 0c65e922368cca53e8a9593f1905c9f6aa1ea6cf Mon Sep 17 00:00:00 2001 +From 5237f244a61ac18b0ca0e4e05fb4086169f93473 Mon Sep 17 00:00:00 2001 From: Robin Murphy <robin.murphy@arm.com> Date: Tue, 20 May 2025 18:10:16 +0100 -Subject: [PATCH 16/17] firmware: smccc: Stub out get_conduit() +Subject: [PATCH 15/16] firmware: smccc: Stub out get_conduit() Various callers use arm_smccc_1_1_get_conduit() to guard their arm_smccc_smc() calls - since the latter is already stubbed out to @@ -1441,10 +1375,10 @@ index 50b47eba7d01..9a8169194be7 100644 2.44.0 -From 5ce44f701822a772a093b73a32c0c0725dc3bb84 Mon Sep 17 00:00:00 2001 +From 7e879ad7c67e0323c85eb07b88ff4306e46f99d8 Mon Sep 17 00:00:00 2001 From: Robin Murphy <robin.murphy@arm.com> Date: Tue, 20 May 2025 18:10:17 +0100 -Subject: [PATCH 17/17] pmdomain: rockchip: Relax SMCCC dependency +Subject: [PATCH 16/16] pmdomain: rockchip: Relax SMCCC dependency Most 32-bit Rockchip platforms do not use PSCI, so having to select ARM_PSCI to satisfy a dependency chain to retain working power domain @@ -1457,12 +1391,12 @@ Signed-off-by: Robin Murphy <robin.murphy@arm.com> 1 file changed, 1 deletion(-) diff --git a/drivers/pmdomain/rockchip/Kconfig b/drivers/pmdomain/rockchip/Kconfig -index 218d43186e5b..ffe5e7b78494 100644 +index 17f2e6fe86b6..b04365e70f06 100644 --- a/drivers/pmdomain/rockchip/Kconfig +++ b/drivers/pmdomain/rockchip/Kconfig -@@ -4,7 +4,6 @@ if ARCH_ROCKCHIP || COMPILE_TEST - config ROCKCHIP_PM_DOMAINS +@@ -5,7 +5,6 @@ config ROCKCHIP_PM_DOMAINS bool "Rockchip generic power domain" + default ARCH_ROCKCHIP depends on PM - depends on HAVE_ARM_SMCCC_DISCOVERY depends on REGULATOR