| author | Urja (ARMLFS builder)
<urja+armlfs@urja.dev> 2025-09-21 09:39:08 UTC |
| committer | Urja (ARMLFS builder)
<urja+armlfs@urja.dev> 2025-09-21 09:39:08 UTC |
| parent | 9c0a9bfdf294ccc9d4e7d1735bf256b25709adfa |
| .SRCINFO | +6 | -6 |
| PKGBUILD | +5 | -5 |
| armlfs.patch | +68 | -4604 |
diff --git a/.SRCINFO b/.SRCINFO index 0e90593..da051f2 100644 --- a/.SRCINFO +++ b/.SRCINFO @@ -1,5 +1,5 @@ pkgbase = linux-armlfs - pkgver = 6.15.8 + pkgver = 6.16.8 pkgrel = 1 url = http://www.kernel.org/ arch = armv7h @@ -28,8 +28,8 @@ pkgbase = linux-armlfs makedepends = sysfsutils makedepends = ncurses options = !strip - source = https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.15.tar.xz - source = https://www.kernel.org/pub/linux/kernel/v6.x/patch-6.15.8.xz + source = https://www.kernel.org/pub/linux/kernel/v6.x/linux-6.16.tar.xz + source = https://www.kernel.org/pub/linux/kernel/v6.x/patch-6.16.8.xz source = armlfs.patch source = kernel.its source = kernel.keyblock @@ -40,9 +40,9 @@ pkgbase = linux-armlfs source = cpupower.service source = usbipd.service source = config - sha256sums = 7586962547803be7ecc4056efc927fb25214548722bd28171172f3599abb9764 - sha256sums = effa3deecc0266054731349ecabb68455f125c7be2f88fd21a841080fd30a4c8 - sha256sums = 5ff44c1b375131c544c67abb72558009b1f772dff0720e82f010712f7af90a52 + sha256sums = 1a4be2fe6b5246aa4ac8987a8a4af34c42a8dd7d08b46ab48516bcc1befbcd83 + sha256sums = b27835c7d685efc3ab770eead7d686a1d8cae4c2cec1a6c1efeb3c6d18bbc7b3 + sha256sums = 77fa64d5f762e7a797bd7824ee8d676974a86c766a8aa50b1eb925f1db9c3d8f sha256sums = 994aee74b13313bdc7c47df4d621c890f5ee52bc18f6c7b658de215c17423b2a sha256sums = 4e708c9ec43ac4a5d718474c9431ba6b6da3e64a9dda6afd2853a9e9e3079ffb sha256sums = bc9e707a86e55a93f423e7bcdae4a25fd470b868e53829b91bbe2ccfbc6da27b diff --git a/PKGBUILD b/PKGBUILD index 5b4b8d1..d8e2321 100644 --- a/PKGBUILD +++ b/PKGBUILD @@ -15,10 +15,10 @@ buildarch=4 _xname= pkgbase=linux-armlfs${_xname} -_srcname=linux-6.15 +_srcname=linux-6.16 _kernelname=${pkgbase#linux} _desc="Veyron Speedy" -pkgver=6.15.8 +pkgver=6.16.8 pkgrel=1 arch=('armv7h') url="http://www.kernel.org/" @@ -333,9 +333,9 @@ package_tmon() { } -sha256sums=('7586962547803be7ecc4056efc927fb25214548722bd28171172f3599abb9764' - 'effa3deecc0266054731349ecabb68455f125c7be2f88fd21a841080fd30a4c8' - '5ff44c1b375131c544c67abb72558009b1f772dff0720e82f010712f7af90a52' +sha256sums=('1a4be2fe6b5246aa4ac8987a8a4af34c42a8dd7d08b46ab48516bcc1befbcd83' + 'b27835c7d685efc3ab770eead7d686a1d8cae4c2cec1a6c1efeb3c6d18bbc7b3' + '77fa64d5f762e7a797bd7824ee8d676974a86c766a8aa50b1eb925f1db9c3d8f' '994aee74b13313bdc7c47df4d621c890f5ee52bc18f6c7b658de215c17423b2a' '4e708c9ec43ac4a5d718474c9431ba6b6da3e64a9dda6afd2853a9e9e3079ffb' 'bc9e707a86e55a93f423e7bcdae4a25fd470b868e53829b91bbe2ccfbc6da27b' diff --git a/armlfs.patch b/armlfs.patch index 7de889d..9309962 100644 --- a/armlfs.patch +++ b/armlfs.patch @@ -1,7 +1,7 @@ -From 6bed53dcccc4201f646d8ed31a431b36e4ab1ae9 Mon Sep 17 00:00:00 2001 +From 6cadf878cb46572b874232c8280976bbdcd9eaab Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 10:30:55 +0000 -Subject: [PATCH 01/34] drivers: clk-rk3288: support for dedicating NPLL to a +Subject: [PATCH 01/17] drivers: clk-rk3288: support for dedicating NPLL to a VOP As controlled by the just introduced dts property. @@ -13,7 +13,7 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 2 files changed, 61 insertions(+), 12 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 90d329216064a..671c786ddbaa1 100644 +index 0a1e017df7c6..f302e321f8ff 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -195,10 +195,14 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; @@ -153,10 +153,10 @@ index 90d329216064a..671c786ddbaa1 100644 pr_err("%s: rockchip clk init failed\n", __func__); iounmap(rk3288_cru_base); diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h -index df2b2d706450f..df85bd94647a8 100644 +index 1e9c3c0d31e3..156cca00f6ea 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h -@@ -624,6 +624,9 @@ struct clk *rockchip_clk_register_muxgrf(const char *name, +@@ -661,6 +661,9 @@ struct clk *rockchip_clk_register_gate_grf(const char *name, #define PNAME(x) static const char *const x[] __initconst @@ -170,10 +170,10 @@ index df2b2d706450f..df85bd94647a8 100644 2.44.0 -From f18c5593477579173f3287829d8f7d5df6395cf6 Mon Sep 17 00:00:00 2001 +From 757e8f0746e735c5bd34ce9fc27a3d995fa77232 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Wed, 22 Aug 2018 18:36:40 +0000 -Subject: [PATCH 02/34] drm: dw_hdmi-rockchip: better clock selection logic and +Subject: [PATCH 02/17] drm: dw_hdmi-rockchip: better clock selection logic and dts-based rate list This contains traces of the following commits from the ChromeOS 3.14 @@ -203,7 +203,7 @@ Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com> 1 file changed, 109 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index f737e7d46e667..0bd62f21d6e57 100644 +index f737e7d46e66..0bd62f21d6e5 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -81,8 +81,13 @@ struct rockchip_hdmi { @@ -466,10 +466,10 @@ index f737e7d46e667..0bd62f21d6e57 100644 2.44.0 -From 1ab4a2fa02e4c861e007569092142a65812c3a84 Mon Sep 17 00:00:00 2001 +From 75bf83b7bf44633989568cb7ff8170e1f6b41829 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 19:00:50 +0000 -Subject: [PATCH 03/34] dts: rk3288: support for dedicating npll to a vop +Subject: [PATCH 03/17] dts: rk3288: support for dedicating npll to a vop Add the VOP DCLKs to the assigned clocks list so their parents can be set in the dts include files for @@ -481,10 +481,10 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 3f1d640afafae..2992c323d5554 100644 +index 42d705b544ec..775f24876be4 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -876,12 +876,14 @@ +@@ -873,12 +873,14 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; @@ -505,10 +505,10 @@ index 3f1d640afafae..2992c323d5554 100644 2.44.0 -From c21a5c40a5664e1c80836b2d682ba68ae3ff210a Mon Sep 17 00:00:00 2001 +From 9d76df2656f8fc2f8920a17f8c4947e6dfdbcdcb Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 27 Aug 2018 19:03:49 +0000 -Subject: [PATCH 04/34] dts: rk3288-veyron-chromebook: dedicate npll to +Subject: [PATCH 04/17] dts: rk3288-veyron-chromebook: dedicate npll to VOP0/HDMI + HDMI rates This enables flexible HDMI rates on the rk3288 chromebooks so that they @@ -522,7 +522,7 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi -index 3677571b4d827..b61a4b0d7015b 100644 +index 3677571b4d82..b61a4b0d7015 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-chromebook.dtsi @@ -83,6 +83,68 @@ @@ -598,10 +598,10 @@ index 3677571b4d827..b61a4b0d7015b 100644 2.44.0 -From cda60bff3c09e31797eb98ddc767217324c7513f Mon Sep 17 00:00:00 2001 +From 510132e0be1cb21ef94a9579ac01f1ce51f6a610 Mon Sep 17 00:00:00 2001 From: SolidHal <hal@halemmerich.com> Date: Sun, 21 Oct 2018 16:40:15 -0500 -Subject: [PATCH 05/34] Added a second reset when having an issue reading the +Subject: [PATCH 05/17] Added a second reset when having an issue reading the emmc. The c201 emmc can be... touchy. Sometimes one full reset isn't @@ -621,7 +621,7 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c -index 4830628510e6e..7658effcb6efe 100644 +index 9cc47bf94804..8ce96fc0b85d 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -1090,6 +1090,7 @@ static unsigned int mmc_blk_data_timeout_ms(struct mmc_host *host, @@ -651,10 +651,10 @@ index 4830628510e6e..7658effcb6efe 100644 2.44.0 -From 81f38f335bcd2fe81e414fc759862236383fc374 Mon Sep 17 00:00:00 2001 +From 1223f85e2f5e74a2dc4975e3fbac470431509aad Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Tue, 9 Oct 2018 22:01:07 +0200 -Subject: [PATCH 06/34] block: partitions: efi: Ignore bizarre Chromebook GPT +Subject: [PATCH 06/17] block: partitions: efi: Ignore bizarre Chromebook GPT partitions This patch is based on @SolidHal work here : @@ -691,7 +691,7 @@ Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr> 2 files changed, 25 insertions(+), 11 deletions(-) diff --git a/block/partitions/efi.c b/block/partitions/efi.c -index 7acba66eed481..087032a4705e7 100644 +index 7acba66eed48..087032a4705e 100644 --- a/block/partitions/efi.c +++ b/block/partitions/efi.c @@ -328,23 +328,34 @@ static gpt_header *alloc_read_gpt_header(struct parsed_partitions *state, @@ -787,7 +787,7 @@ index 7acba66eed481..087032a4705e7 100644 } diff --git a/block/partitions/efi.h b/block/partitions/efi.h -index 84b9f36b9e479..09726227e8913 100644 +index 84b9f36b9e47..09726227e891 100644 --- a/block/partitions/efi.h +++ b/block/partitions/efi.h @@ -26,7 +26,8 @@ @@ -804,10 +804,10 @@ index 84b9f36b9e479..09726227e8913 100644 2.44.0 -From 2bb127ea62ca2aa17ac119d6f735e465bad7885a Mon Sep 17 00:00:00 2001 +From eefd1379520088d562fc2ce000e7f4764cf0ab10 Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Tue, 30 Oct 2018 22:44:54 +0100 -Subject: [PATCH 07/34] mmc: Added a flag to disable cache flush during reset +Subject: [PATCH 07/17] mmc: Added a flag to disable cache flush during reset The ASUS Chromebook suffer from 10 minutes long hang, when trying to flush the cache of the eMMC, in order to recover from eMMC init @@ -827,7 +827,7 @@ Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr> 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c -index dacb5bd9bb714..04703ce624abe 100644 +index f14671ea5716..c5f8b935f036 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -405,6 +405,8 @@ int mmc_of_parse(struct mmc_host *host) @@ -840,10 +840,10 @@ index dacb5bd9bb714..04703ce624abe 100644 /* Must be after "non-removable" check */ if (device_property_read_u32(dev, "fixed-emmc-driver-type", &drv_type) == 0) { diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c -index 1522fd2b517dd..0a970bc258f23 100644 +index 5be9b42d5057..5e5cfd7c23b3 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c -@@ -2242,6 +2242,12 @@ static int mmc_runtime_resume(struct mmc_host *host) +@@ -2269,6 +2269,12 @@ static int mmc_runtime_resume(struct mmc_host *host) return 0; } @@ -853,10 +853,10 @@ index 1522fd2b517dd..0a970bc258f23 100644 + return (host->caps2 & MMC_CAP2_NO_RECOVERY_CACHE_FLUSH) == 0; +} + - static int mmc_can_reset(struct mmc_card *card) + static bool mmc_card_can_reset(struct mmc_card *card) { u8 rst_n_function; -@@ -2256,11 +2262,15 @@ static int _mmc_hw_reset(struct mmc_host *host) +@@ -2281,11 +2287,15 @@ static int _mmc_hw_reset(struct mmc_host *host) { struct mmc_card *card = host->card; @@ -875,9 +875,9 @@ index 1522fd2b517dd..0a970bc258f23 100644 + _mmc_flush_cache(host); if ((host->caps & MMC_CAP_HW_RESET) && host->ops->card_hw_reset && - mmc_can_reset(card)) { + mmc_card_can_reset(card)) { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h -index 68f09a955a902..eb7dbf0f9b101 100644 +index 68f09a955a90..eb7dbf0f9b10 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -459,6 +459,7 @@ struct mmc_host { @@ -892,10 +892,10 @@ index 68f09a955a902..eb7dbf0f9b101 100644 2.44.0 -From 51e46e760935e8471ad4ca27203b62c7ef79bdbe Mon Sep 17 00:00:00 2001 +From 90e6ee443cab5e533a82f63c18c5f6d192301734 Mon Sep 17 00:00:00 2001 From: "Miouyouyou (Myy)" <myy@miouyouyou.fr> Date: Thu, 1 Nov 2018 21:31:26 +0100 -Subject: [PATCH 08/34] arm: dts: veyron: Added a flag to disable cache flush +Subject: [PATCH 08/17] arm: dts: veyron: Added a flag to disable cache flush during reset Flushing the MMC cache of ASUS Chromebooks during initialization or @@ -910,7 +910,7 @@ Signed-off-by: Miouyouyou (Myy) <myy@miouyouyou.fr> 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi -index 260d6c92cfd11..08ce8bfb70b21 100644 +index 260d6c92cfd1..08ce8bfb70b2 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron.dtsi @@ -157,6 +157,7 @@ @@ -925,10 +925,10 @@ index 260d6c92cfd11..08ce8bfb70b21 100644 2.44.0 -From 9f16cf507ee459ad5b69ae9acee43fa227749601 Mon Sep 17 00:00:00 2001 +From 7e20805366ee2a8cb3c61d47470ebe443ff30c0a Mon Sep 17 00:00:00 2001 From: Hal Emmerich <hal@halemmerich.com> Date: Wed, 21 Aug 2019 16:52:41 -0500 -Subject: [PATCH 09/34] Fix ath9k dwc2 init frame overruns +Subject: [PATCH 09/17] Fix ath9k dwc2 init frame overruns [ by Urja Rannikko: changed to log message to something more sensible. ] @@ -944,7 +944,7 @@ communicate properly. In my testing this did not impact network speeds. 1 file changed, 10 insertions(+) diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c -index b0098792dd225..73d7c7754bc57 100644 +index 904fe0632b34..6a9ecc809814 100644 --- a/drivers/usb/dwc2/hcd_queue.c +++ b/drivers/usb/dwc2/hcd_queue.c @@ -1491,6 +1491,16 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, @@ -968,10 +968,10 @@ index b0098792dd225..73d7c7754bc57 100644 2.44.0 -From d7c754d3ba777e1481a5eca746d2b8ca45a36080 Mon Sep 17 00:00:00 2001 +From 88a0b50cf2acf01182b9367c496ee1697024496d Mon Sep 17 00:00:00 2001 From: barzur <boris@konbu.org> Date: Fri, 12 Jul 2019 11:33:32 +0900 -Subject: [PATCH 10/34] usb/dwc2/hcd: channel halt may not be an error +Subject: [PATCH 10/17] usb/dwc2/hcd: channel halt may not be an error Truncating the data was causing null pointer exceptions in memcpy, let's be more careful. @@ -1008,7 +1008,7 @@ meantime I'm including it here. 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c -index 60ef8092259a9..a190524108e85 100644 +index 30eb8506617c..725012cf03d7 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -2457,7 +2457,8 @@ static void dwc2_free_dma_aligned_buffer(struct urb *urb) @@ -1022,7 +1022,7 @@ index 60ef8092259a9..a190524108e85 100644 kfree(urb->transfer_buffer); urb->transfer_buffer = stored_xfer_buffer; diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c -index 5c7538d498dd1..96dc5d8115d2c 100644 +index 5c7538d498dd..96dc5d8115d2 100644 --- a/drivers/usb/dwc2/hcd_intr.c +++ b/drivers/usb/dwc2/hcd_intr.c @@ -1935,7 +1935,8 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, @@ -1039,10 +1039,10 @@ index 5c7538d498dd1..96dc5d8115d2c 100644 2.44.0 -From 0c01f1be5ff7f61787f4188f64780e09ecda4f49 Mon Sep 17 00:00:00 2001 +From 8356dcc57ec0caff95f9310268955011b7c120dd Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 8 Oct 2019 11:03:37 +0000 -Subject: [PATCH 11/34] drm/panel: edp: Extend Innolux N116BGE mode info for +Subject: [PATCH 11/17] drm/panel: edp: Extend Innolux N116BGE mode info for ~60Hz from 74.25 Mhz Signed-off-by: Urja Rannikko <urjaman@gmail.com> @@ -1051,10 +1051,10 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c -index 52028c8f8988d..cc29548273c2d 100644 +index 90e8c154a978..56af11a9cf1e 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c -@@ -1295,16 +1295,25 @@ static const struct panel_desc innolux_n116bca_ea1 = { +@@ -1294,16 +1294,25 @@ static const struct panel_desc innolux_n116bca_ea1 = { * porch, back porch, or sync length. For now we'll leave a single setting * here which allows a bit of tweaking of the pixel clock at the expense of * refresh rate. @@ -1086,10 +1086,10 @@ index 52028c8f8988d..cc29548273c2d 100644 2.44.0 -From 24a68df9540f3c4224747b878ac16570eb6f5f84 Mon Sep 17 00:00:00 2001 +From e8640dcdff3568b6333af4a3dc4ccd3f3e5303d5 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 8 Oct 2019 11:12:33 +0000 -Subject: [PATCH 12/34] ARM: dts: rockchip: Adjust rk3288-veyron n116bge mode +Subject: [PATCH 12/17] ARM: dts: rockchip: Adjust rk3288-veyron n116bge mode for ~60Hz This is an experimental mode that gets very close to 60Hz (60.00067..) @@ -1102,7 +1102,7 @@ Signed-off-by: Urja Rannikko <urjaman@gmail.com> 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi -index fb031964fa2bb..128176b7c3721 100644 +index fb031964fa2b..128176b7c372 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-veyron-edp.dtsi @@ -62,13 +62,13 @@ @@ -1125,10 +1125,10 @@ index fb031964fa2bb..128176b7c3721 100644 2.44.0 -From a13b6ea84d6ca222ce5007ef358bd4312b68e318 Mon Sep 17 00:00:00 2001 +From de3b199c3ed76a2fae7d05f77aa1392745ab1a15 Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Mon, 25 Dec 2023 18:06:10 +0200 -Subject: [PATCH 13/34] dts: veyron: bluetooth: disable dma on uart0 +Subject: [PATCH 13/17] dts: veyron: bluetooth: disable dma on uart0 I just pulled this off the internet ;) https://codeberg.org/petms/linux-veyron-patches-and-apkbuild @@ -1137,10 +1137,10 @@ https://codeberg.org/petms/linux-veyron-patches-and-apkbuild 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 2992c323d5554..949bc1829c8fa 100644 +index 775f24876be4..a19bf9f83a4d 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -387,8 +387,6 @@ +@@ -384,8 +384,6 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; @@ -1153,4546 +1153,10 @@ index 2992c323d5554..949bc1829c8fa 100644 2.44.0 -From a63dd1dc100aef2dbcaeda32ece6eca6cb89faa5 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:00 +0000 -Subject: [PATCH 14/34] media: v4l2-common: Add helpers to calculate - bytesperline and sizeimage - -Add helper functions to calculate plane bytesperline and sizeimage, -these new helpers consider bpp div, block width and height when -calculating plane bytesperline and sizeimage. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/media/v4l2-core/v4l2-common.c | 78 +++++++++++++-------------- - 1 file changed, 39 insertions(+), 39 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index e4b2de3833ee3..d9b0766f3073f 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -357,6 +357,34 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf - return info->block_h[plane]; - } - -+static inline unsigned int v4l2_format_plane_width(const struct v4l2_format_info *info, int plane, -+ unsigned int width) -+{ -+ unsigned int hdiv = plane ? info->hdiv : 1; -+ unsigned int aligned_width = -+ ALIGN(width, v4l2_format_block_width(info, plane)); -+ -+ return DIV_ROUND_UP(aligned_width, hdiv) * -+ info->bpp[plane] / info->bpp_div[plane]; -+} -+ -+static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane, -+ unsigned int height) -+{ -+ unsigned int vdiv = plane ? info->vdiv : 1; -+ unsigned int aligned_height = -+ ALIGN(height, v4l2_format_block_height(info, plane)); -+ -+ return DIV_ROUND_UP(aligned_height, vdiv); -+} -+ -+static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane, -+ unsigned int width, unsigned int height) -+{ -+ return v4l2_format_plane_width(info, plane, width) * -+ v4l2_format_plane_height(info, plane, height); -+} -+ - void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, - const struct v4l2_frmsize_stepwise *frmsize) - { -@@ -392,37 +420,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, - - if (info->mem_planes == 1) { - plane = &pixfmt->plane_fmt[0]; -- plane->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; -+ plane->bytesperline = v4l2_format_plane_width(info, 0, width); - plane->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- plane->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; -- } -+ for (i = 0; i < info->comp_planes; i++) -+ plane->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - } else { - for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- - plane = &pixfmt->plane_fmt[i]; - plane->bytesperline = -- info->bpp[i] * DIV_ROUND_UP(aligned_width, hdiv) / info->bpp_div[i]; -- plane->sizeimage = -- plane->bytesperline * DIV_ROUND_UP(aligned_height, vdiv); -+ v4l2_format_plane_width(info, i, width); -+ plane->sizeimage = plane->bytesperline * -+ v4l2_format_plane_height(info, i, height); - } - } - return 0; -@@ -446,22 +456,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, - pixfmt->width = width; - pixfmt->height = height; - pixfmt->pixelformat = pixelformat; -- pixfmt->bytesperline = ALIGN(width, v4l2_format_block_width(info, 0)) * info->bpp[0] / info->bpp_div[0]; -+ pixfmt->bytesperline = v4l2_format_plane_width(info, 0, width); - pixfmt->sizeimage = 0; - -- for (i = 0; i < info->comp_planes; i++) { -- unsigned int hdiv = (i == 0) ? 1 : info->hdiv; -- unsigned int vdiv = (i == 0) ? 1 : info->vdiv; -- unsigned int aligned_width; -- unsigned int aligned_height; -- -- aligned_width = ALIGN(width, v4l2_format_block_width(info, i)); -- aligned_height = ALIGN(height, v4l2_format_block_height(info, i)); -- -- pixfmt->sizeimage += info->bpp[i] * -- DIV_ROUND_UP(aligned_width, hdiv) * -- DIV_ROUND_UP(aligned_height, vdiv) / info->bpp_div[i]; -- } -+ for (i = 0; i < info->comp_planes; i++) -+ pixfmt->sizeimage += -+ v4l2_format_plane_size(info, i, width, height); - return 0; - } - EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt); --- -2.44.0 - - -From e8e88a229494b1dc10e43c1141228bd61f052d35 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:01 +0000 -Subject: [PATCH 15/34] media: v4l2: Add NV15 and NV20 pixel formats - -Add NV15 and NV20 pixel formats used by the Rockchip Video Decoder for -10-bit buffers. - -NV15 and NV20 is 10-bit 4:2:0/4:2:2 semi-planar YUV formats similar to -NV12 and NV16, using 10-bit components with no padding between each -component. Instead, a group of 4 luminance/chrominance samples are -stored over 5 bytes in little endian order: - -YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes - -The '15' and '20' suffix refers to the optimum effective bits per pixel -which is achieved when the total number of luminance samples is a -multiple of 8 for NV15 and 4 for NV20. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - .../media/v4l/pixfmt-yuv-planar.rst | 128 ++++++++++++++++++ - drivers/media/v4l2-core/v4l2-common.c | 2 + - drivers/media/v4l2-core/v4l2-ioctl.c | 2 + - include/uapi/linux/videodev2.h | 2 + - 4 files changed, 134 insertions(+) - -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst -index b788f69338554..22cad8c9726bf 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst -@@ -79,6 +79,13 @@ All components are stored with the same number of bits per component. - - Cr, Cb - - Yes - - Linear -+ * - V4L2_PIX_FMT_NV15 -+ - 'NV15' -+ - 10 -+ - 4:2:0 -+ - Cb, Cr -+ - Yes -+ - Linear - * - V4L2_PIX_FMT_NV12M - - 'NM12' - - 8 -@@ -172,6 +179,13 @@ All components are stored with the same number of bits per component. - - Cr, Cb - - Yes - - Linear -+ * - V4L2_PIX_FMT_NV20 -+ - 'NV20' -+ - 10 -+ - 4:2:2 -+ - Cb, Cr -+ - Yes -+ - Linear - * - V4L2_PIX_FMT_NV16M - - 'NM16' - - 8 -@@ -302,6 +316,57 @@ of the luma plane. - - Cr\ :sub:`11` - - -+.. _V4L2-PIX-FMT-NV15: -+ -+NV15 -+---- -+ -+Semi-planar 10-bit YUV 4:2:0 format similar to NV12, using 10-bit components -+with no padding between each component. A group of 4 components are stored over -+5 bytes in little endian order. -+ -+.. flat-table:: Sample 4x4 NV15 Image (1 byte per cell) -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - start + 0: -+ - Y'\ :sub:`00[7:0]` -+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]` -+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]` -+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]` -+ - Y'\ :sub:`03[9:2]` -+ * - start + 5: -+ - Y'\ :sub:`10[7:0]` -+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]` -+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]` -+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]` -+ - Y'\ :sub:`13[9:2]` -+ * - start + 10: -+ - Y'\ :sub:`20[7:0]` -+ - Y'\ :sub:`21[5:0]`\ Y'\ :sub:`20[9:8]` -+ - Y'\ :sub:`22[3:0]`\ Y'\ :sub:`21[9:6]` -+ - Y'\ :sub:`23[1:0]`\ Y'\ :sub:`22[9:4]` -+ - Y'\ :sub:`23[9:2]` -+ * - start + 15: -+ - Y'\ :sub:`30[7:0]` -+ - Y'\ :sub:`31[5:0]`\ Y'\ :sub:`30[9:8]` -+ - Y'\ :sub:`32[3:0]`\ Y'\ :sub:`31[9:6]` -+ - Y'\ :sub:`33[1:0]`\ Y'\ :sub:`32[9:4]` -+ - Y'\ :sub:`33[9:2]` -+ * - start + 20: -+ - Cb\ :sub:`00[7:0]` -+ - Cr\ :sub:`00[5:0]`\ Cb\ :sub:`00[9:8]` -+ - Cb\ :sub:`01[3:0]`\ Cr\ :sub:`00[9:6]` -+ - Cr\ :sub:`01[1:0]`\ Cb\ :sub:`01[9:4]` -+ - Cr\ :sub:`01[9:2]` -+ * - start + 25: -+ - Cb\ :sub:`10[7:0]` -+ - Cr\ :sub:`10[5:0]`\ Cb\ :sub:`10[9:8]` -+ - Cb\ :sub:`11[3:0]`\ Cr\ :sub:`10[9:6]` -+ - Cr\ :sub:`11[1:0]`\ Cb\ :sub:`11[9:4]` -+ - Cr\ :sub:`11[9:2]` -+ -+ - .. _V4L2-PIX-FMT-NV12MT: - .. _V4L2-PIX-FMT-NV12MT-16X16: - .. _V4L2-PIX-FMT-NV12-4L4: -@@ -631,6 +696,69 @@ number of lines as the luma plane. - - Cr\ :sub:`32` - - -+.. _V4L2-PIX-FMT-NV20: -+ -+NV20 -+---- -+ -+Semi-planar 10-bit YUV 4:2:2 format similar to NV16, using 10-bit components -+with no padding between each component. A group of 4 components are stored over -+5 bytes in little endian order. -+ -+.. flat-table:: Sample 4x4 NV20 Image (1 byte per cell) -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - start + 0: -+ - Y'\ :sub:`00[7:0]` -+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]` -+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]` -+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]` -+ - Y'\ :sub:`03[9:2]` -+ * - start + 5: -+ - Y'\ :sub:`10[7:0]` -+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]` -+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]` -+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]` -+ - Y'\ :sub:`13[9:2]` -+ * - start + 10: -+ - Y'\ :sub:`20[7:0]` -+ - Y'\ :sub:`21[5:0]`\ Y'\ :sub:`20[9:8]` -+ - Y'\ :sub:`22[3:0]`\ Y'\ :sub:`21[9:6]` -+ - Y'\ :sub:`23[1:0]`\ Y'\ :sub:`22[9:4]` -+ - Y'\ :sub:`23[9:2]` -+ * - start + 15: -+ - Y'\ :sub:`30[7:0]` -+ - Y'\ :sub:`31[5:0]`\ Y'\ :sub:`30[9:8]` -+ - Y'\ :sub:`32[3:0]`\ Y'\ :sub:`31[9:6]` -+ - Y'\ :sub:`33[1:0]`\ Y'\ :sub:`32[9:4]` -+ - Y'\ :sub:`33[9:2]` -+ * - start + 20: -+ - Cb\ :sub:`00[7:0]` -+ - Cr\ :sub:`00[5:0]`\ Cb\ :sub:`00[9:8]` -+ - Cb\ :sub:`01[3:0]`\ Cr\ :sub:`00[9:6]` -+ - Cr\ :sub:`01[1:0]`\ Cb\ :sub:`01[9:4]` -+ - Cr\ :sub:`01[9:2]` -+ * - start + 25: -+ - Cb\ :sub:`10[7:0]` -+ - Cr\ :sub:`10[5:0]`\ Cb\ :sub:`10[9:8]` -+ - Cb\ :sub:`11[3:0]`\ Cr\ :sub:`10[9:6]` -+ - Cr\ :sub:`11[1:0]`\ Cb\ :sub:`11[9:4]` -+ - Cr\ :sub:`11[9:2]` -+ * - start + 30: -+ - Cb\ :sub:`20[7:0]` -+ - Cr\ :sub:`20[5:0]`\ Cb\ :sub:`20[9:8]` -+ - Cb\ :sub:`21[3:0]`\ Cr\ :sub:`20[9:6]` -+ - Cr\ :sub:`21[1:0]`\ Cb\ :sub:`21[9:4]` -+ - Cr\ :sub:`21[9:2]` -+ * - start + 35: -+ - Cb\ :sub:`30[7:0]` -+ - Cr\ :sub:`30[5:0]`\ Cb\ :sub:`30[9:8]` -+ - Cb\ :sub:`31[3:0]`\ Cr\ :sub:`30[9:6]` -+ - Cr\ :sub:`31[1:0]`\ Cb\ :sub:`31[9:4]` -+ - Cr\ :sub:`31[9:2]` -+ -+ - .. _V4L2-PIX-FMT-NV24: - .. _V4L2-PIX-FMT-NV42: - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index d9b0766f3073f..f685714b05776 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -277,8 +277,10 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) - /* YUV planar formats */ - { .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2 }, - { .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2 }, -+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 10, 0, 0 }, .bpp_div = { 4, 4, 1, 1 }, .hdiv = 2, .vdiv = 2 }, - { .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 }, -+ { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 10, 0, 0 }, .bpp_div = { 4, 4, 1, 1 }, .hdiv = 2, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 1 }, -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index a16fb44c7246e..e97881f74c0d7 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1363,8 +1363,10 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_YUV48_12: descr = "12-bit YUV 4:4:4 Packed"; break; - case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break; - case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break; -+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break; - case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break; - case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break; -+ case V4L2_PIX_FMT_NV20: descr = "10-bit Y/UV 4:2:2 (Packed)"; break; - case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break; - case V4L2_PIX_FMT_NV42: descr = "Y/VU 4:4:4"; break; - case V4L2_PIX_FMT_P010: descr = "10-bit Y/UV 4:2:0"; break; -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index af86ece741e94..ca7b3e8863ca3 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -651,8 +651,10 @@ struct v4l2_pix_format { - /* two planes -- one Y, one Cr + Cb interleaved */ - #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ - #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ -+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ - #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ - #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ -+#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */ - #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ - #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ - #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */ --- -2.44.0 - - -From e632dfc69c4ddd44cc206e67ec74849144717765 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:02 +0000 -Subject: [PATCH 16/34] media: rkvdec: h264: Use bytesperline and buffer height - as virstride - -Use bytesperline and buffer height to calculate the strides configured. - -This does not really change anything other than ensuring the -bytesperline that is signaled to userspace matches what is configured -in HW. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 4fc167b42cf0c..7a1e76d423df5 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx, - dma_addr_t rlc_addr; - dma_addr_t refer_addr; - u32 rlc_len; -- u32 hor_virstride = 0; -- u32 ver_virstride = 0; -- u32 y_virstride = 0; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; - u32 yuv_virstride = 0; - u32 offset; - dma_addr_t dst_addr; -@@ -909,16 +909,16 @@ static void config_registers(struct rkvdec_ctx *ctx, - - f = &ctx->decoded_fmt; - dst_fmt = &f->fmt.pix_mp; -- hor_virstride = (sps->bit_depth_luma_minus8 + 8) * dst_fmt->width / 8; -- ver_virstride = round_up(dst_fmt->height, 16); -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; - y_virstride = hor_virstride * ver_virstride; - - if (sps->chroma_format_idc == 0) - yuv_virstride = y_virstride; - else if (sps->chroma_format_idc == 1) -- yuv_virstride += y_virstride + y_virstride / 2; -+ yuv_virstride = y_virstride + y_virstride / 2; - else if (sps->chroma_format_idc == 2) -- yuv_virstride += 2 * y_virstride; -+ yuv_virstride = 2 * y_virstride; - - reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | - RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | --- -2.44.0 - - -From d671cf412cb1b1f08eb6ac7c26285b10e325ab9f Mon Sep 17 00:00:00 2001 -From: Alex Bee <knaerzche@gmail.com> -Date: Sun, 5 Nov 2023 16:55:03 +0000 -Subject: [PATCH 17/34] media: rkvdec: h264: Don't hardcode SPS/PPS parameters - -Some SPS/PPS parameters are currently hardcoded in the driver even -though they exist in the stable uapi controls. - -Use values from SPS/PPS controls instead of hardcoding them. - -Signed-off-by: Alex Bee <knaerzche@gmail.com> -[jonas@kwiboo.se: constraint_set_flags condition, commit message] -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 13 +++++++------ - 1 file changed, 7 insertions(+), 6 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 7a1e76d423df5..8bce8902b8dda 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - - #define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) - /* write sps */ -- WRITE_PPS(0xf, SEQ_PARAMETER_SET_ID); -- WRITE_PPS(0xff, PROFILE_IDC); -- WRITE_PPS(1, CONSTRAINT_SET3_FLAG); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->profile_idc, PROFILE_IDC); -+ WRITE_PPS(!!(sps->constraint_set_flags & (1 << 3)), CONSTRAINT_SET3_FLAG); - WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); - WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); - WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); -- WRITE_PPS(0, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS), -+ QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG); - WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); - WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); - WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE); -@@ -688,8 +689,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - DIRECT_8X8_INFERENCE_FLAG); - - /* write pps */ -- WRITE_PPS(0xff, PIC_PARAMETER_SET_ID); -- WRITE_PPS(0x1f, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), - ENTROPY_CODING_MODE_FLAG); - WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), --- -2.44.0 - - -From 56ff8145b42b349da072c2c82b9a8a6f69386789 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:04 +0000 -Subject: [PATCH 18/34] media: rkvdec: h264: Remove SPS validation at streaming - start - -SPS parameters is validated in try_ctrl() ops so there is no need to -re-validate when streaming starts. - -Remove the unnecessary call to validate sps at streaming start. - -Suggested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 19 ++----------------- - 1 file changed, 2 insertions(+), 17 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 8bce8902b8dda..815d5359ddd5c 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -1070,17 +1070,6 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx) - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_h264_priv_tbl *priv_tbl; - struct rkvdec_h264_ctx *h264_ctx; -- struct v4l2_ctrl *ctrl; -- int ret; -- -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_H264_SPS); -- if (!ctrl) -- return -EINVAL; -- -- ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -- if (ret) -- return ret; - - h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); - if (!h264_ctx) -@@ -1089,8 +1078,8 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx) - priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), - &h264_ctx->priv_tbl.dma, GFP_KERNEL); - if (!priv_tbl) { -- ret = -ENOMEM; -- goto err_free_ctx; -+ kfree(h264_ctx); -+ return -ENOMEM; - } - - h264_ctx->priv_tbl.size = sizeof(*priv_tbl); -@@ -1100,10 +1089,6 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx) - - ctx->priv = h264_ctx; - return 0; -- --err_free_ctx: -- kfree(h264_ctx); -- return ret; - } - - static void rkvdec_h264_stop(struct rkvdec_ctx *ctx) --- -2.44.0 - - -From 2892fa27e4347a2bf1f3f3af18429c2d839eead1 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:05 +0000 -Subject: [PATCH 19/34] media: rkvdec: Extract rkvdec_fill_decoded_pixfmt into - helper - -Extract call to v4l2_fill_pixfmt_mp() and ajusting of sizeimage into a -helper. Replace current code with a call to the new helper. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec.c | 27 ++++++++++++++------------- - 1 file changed, 14 insertions(+), 13 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 65befffc35696..4857410a20d0c 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -27,6 +27,16 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - -+static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, -+ struct v4l2_pix_format_mplane *pix_mp) -+{ -+ v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -+ pix_mp->width, pix_mp->height); -+ pix_mp->plane_fmt[0].sizeimage += 128 * -+ DIV_ROUND_UP(pix_mp->width, 16) * -+ DIV_ROUND_UP(pix_mp->height, 16); -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -192,13 +202,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -- v4l2_fill_pixfmt_mp(&f->fmt.pix_mp, -- ctx->coded_fmt_desc->decoded_fmts[0], -- ctx->coded_fmt.fmt.pix_mp.width, -- ctx->coded_fmt.fmt.pix_mp.height); -- f->fmt.pix_mp.plane_fmt[0].sizeimage += 128 * -- DIV_ROUND_UP(f->fmt.pix_mp.width, 16) * -- DIV_ROUND_UP(f->fmt.pix_mp.height, 16); -+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; -+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); - } - - static int rkvdec_enum_framesizes(struct file *file, void *priv, -@@ -270,12 +276,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - &pix_mp->height, - &coded_desc->frmsize); - -- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -- pix_mp->plane_fmt[0].sizeimage += -- 128 * -- DIV_ROUND_UP(pix_mp->width, 16) * -- DIV_ROUND_UP(pix_mp->height, 16); -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); - pix_mp->field = V4L2_FIELD_NONE; - - return 0; --- -2.44.0 - - -From 2225cda5aaab9ce2b3185941afbf5a07d0003cfa Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:06 +0000 -Subject: [PATCH 20/34] media: rkvdec: Move rkvdec_reset_decoded_fmt helper - -Move rkvdec_reset_decoded_fmt() and the called rkvdec_reset_fmt() helper -functions in preparation for adding a new caller in an upcoming patch. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec.c | 46 +++++++++++++-------------- - 1 file changed, 23 insertions(+), 23 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 4857410a20d0c..fd5a8a78070ef 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -37,6 +37,29 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - DIV_ROUND_UP(pix_mp->height, 16); - } - -+static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f, -+ u32 fourcc) -+{ -+ memset(f, 0, sizeof(*f)); -+ f->fmt.pix_mp.pixelformat = fourcc; -+ f->fmt.pix_mp.field = V4L2_FIELD_NONE; -+ f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; -+ f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; -+ f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; -+ f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; -+} -+ -+static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) -+{ -+ struct v4l2_format *f = &ctx->decoded_fmt; -+ -+ rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); -+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -+ f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -+ f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; -+ rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -169,18 +192,6 @@ rkvdec_find_coded_fmt_desc(u32 fourcc) - return NULL; - } - --static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f, -- u32 fourcc) --{ -- memset(f, 0, sizeof(*f)); -- f->fmt.pix_mp.pixelformat = fourcc; -- f->fmt.pix_mp.field = V4L2_FIELD_NONE; -- f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; -- f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; -- f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; -- f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; --} -- - static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->coded_fmt; -@@ -196,17 +207,6 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - ctx->coded_fmt_desc->ops->adjust_fmt(ctx, f); - } - --static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) --{ -- struct v4l2_format *f = &ctx->decoded_fmt; -- -- rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); -- f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; -- f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -- f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; -- rkvdec_fill_decoded_pixfmt(ctx, &f->fmt.pix_mp); --} -- - static int rkvdec_enum_framesizes(struct file *file, void *priv, - struct v4l2_frmsizeenum *fsize) - { --- -2.44.0 - - -From ced65acb549ef7d00c3e4383e4c20ebc381bf581 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:07 +0000 -Subject: [PATCH 21/34] media: rkvdec: Extract decoded format enumeration into - helper - -Add a rkvdec_is_valid_fmt() helper that check if a fourcc is a supported -CAPTURE format, and a rkvdec_enum_decoded_fmt() helper that enumerate -valid formats. - -This move current code into helper functions in preparation for adding -CAPTURE format filtering and validation in next patch. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec.c | 49 +++++++++++++++++++-------- - 1 file changed, 35 insertions(+), 14 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index fd5a8a78070ef..938a8e3e5c768 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -27,6 +27,32 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - -+static u32 rkvdec_enum_decoded_fmt(struct rkvdec_ctx *ctx, int index) -+{ -+ const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ -+ if (WARN_ON(!desc)) -+ return 0; -+ -+ if (index >= desc->num_decoded_fmts) -+ return 0; -+ -+ return desc->decoded_fmts[index]; -+} -+ -+static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc) -+{ -+ const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ unsigned int i; -+ -+ for (i = 0; i < desc->num_decoded_fmts; i++) { -+ if (desc->decoded_fmts[i] == fourcc) -+ return true; -+ } -+ -+ return false; -+} -+ - static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) - { -@@ -52,8 +78,10 @@ static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f, - static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->decoded_fmt; -+ u32 fourcc; - -- rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); -+ fourcc = rkvdec_enum_decoded_fmt(ctx, 0); -+ rkvdec_reset_fmt(ctx, f, fourcc); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; - f->fmt.pix_mp.height = ctx->coded_fmt.fmt.pix_mp.height; -@@ -250,7 +278,6 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - const struct rkvdec_coded_fmt_desc *coded_desc; -- unsigned int i; - - /* - * The codec context should point to a coded format desc, if the format -@@ -261,13 +288,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!coded_desc)) - return -EINVAL; - -- for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -- break; -- } -- -- if (i == coded_desc->num_decoded_fmts) -- pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat)) -+ pix_mp->pixelformat = rkvdec_enum_decoded_fmt(ctx, 0); - - /* Always apply the frmsize constraint of the coded end. */ - pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -431,14 +453,13 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); -+ u32 fourcc; - -- if (WARN_ON(!ctx->coded_fmt_desc)) -- return -EINVAL; -- -- if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) -+ fourcc = rkvdec_enum_decoded_fmt(ctx, f->index); -+ if (!fourcc) - return -EINVAL; - -- f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index]; -+ f->pixelformat = fourcc; - return 0; - } - --- -2.44.0 - - -From 87477613f98da1fde1a831bdc7ce80cc35807ab4 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:08 +0000 -Subject: [PATCH 22/34] media: rkvdec: Add image format concept - -Add an enum rkvdec_image_fmt used to signal an image format, e.g. -4:2:0 8-bit, 4:2:0 10-bit or any. - -Tag each supported CAPUTRE format with an image format and use this tag -to filter out unsupported CAPTURE formats. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec.c | 45 ++++++++++++++++++++------- - drivers/staging/media/rkvdec/rkvdec.h | 13 +++++++- - 2 files changed, 45 insertions(+), 13 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 938a8e3e5c768..6614a9f777d59 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -27,26 +27,42 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - --static u32 rkvdec_enum_decoded_fmt(struct rkvdec_ctx *ctx, int index) -+static inline bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1, -+ enum rkvdec_image_fmt fmt2) -+{ -+ return fmt1 == fmt2 || fmt2 == RKVDEC_IMG_FMT_ANY || -+ fmt1 == RKVDEC_IMG_FMT_ANY; -+} -+ -+static u32 rkvdec_enum_decoded_fmt(struct rkvdec_ctx *ctx, int index, -+ enum rkvdec_image_fmt image_fmt) - { - const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ unsigned int i, j; - - if (WARN_ON(!desc)) - return 0; - -- if (index >= desc->num_decoded_fmts) -- return 0; -+ for (i = 0, j = 0; i < desc->num_decoded_fmts; i++) { -+ if (rkvdec_image_fmt_match(desc->decoded_fmts[i].image_fmt, -+ image_fmt) && -+ index == j++) -+ return desc->decoded_fmts[i].fourcc; -+ } - -- return desc->decoded_fmts[index]; -+ return 0; - } - --static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc) -+static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc, -+ enum rkvdec_image_fmt image_fmt) - { - const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; - unsigned int i; - - for (i = 0; i < desc->num_decoded_fmts; i++) { -- if (desc->decoded_fmts[i] == fourcc) -+ if (rkvdec_image_fmt_match(desc->decoded_fmts[i].image_fmt, -+ image_fmt) && -+ desc->decoded_fmts[i].fourcc == fourcc) - return true; - } - -@@ -80,7 +96,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - struct v4l2_format *f = &ctx->decoded_fmt; - u32 fourcc; - -- fourcc = rkvdec_enum_decoded_fmt(ctx, 0); -+ fourcc = rkvdec_enum_decoded_fmt(ctx, 0, ctx->image_fmt); - rkvdec_reset_fmt(ctx, f, fourcc); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -@@ -149,8 +165,11 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const u32 rkvdec_h264_vp9_decoded_fmts[] = { -- V4L2_PIX_FMT_NV12, -+static const struct rkvdec_decoded_fmt_desc rkvdec_h264_vp9_decoded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -+ }, - }; - - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { -@@ -288,8 +307,9 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!coded_desc)) - return -EINVAL; - -- if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat)) -- pix_mp->pixelformat = rkvdec_enum_decoded_fmt(ctx, 0); -+ if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat, ctx->image_fmt)) -+ pix_mp->pixelformat = rkvdec_enum_decoded_fmt(ctx, 0, -+ ctx->image_fmt); - - /* Always apply the frmsize constraint of the coded end. */ - pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -406,6 +426,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, - * - * Note that this will propagates any size changes to the decoded format. - */ -+ ctx->image_fmt = RKVDEC_IMG_FMT_ANY; - rkvdec_reset_decoded_fmt(ctx); - - /* Propagate colorspace information to capture. */ -@@ -455,7 +476,7 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - u32 fourcc; - -- fourcc = rkvdec_enum_decoded_fmt(ctx, f->index); -+ fourcc = rkvdec_enum_decoded_fmt(ctx, f->index, ctx->image_fmt); - if (!fourcc) - return -EINVAL; - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 633335ebb9c49..6f8cf50c5d99a 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -75,13 +75,23 @@ struct rkvdec_coded_fmt_ops { - int (*try_ctrl)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); - }; - -+enum rkvdec_image_fmt { -+ RKVDEC_IMG_FMT_ANY = 0, -+ RKVDEC_IMG_FMT_420_8BIT, -+}; -+ -+struct rkvdec_decoded_fmt_desc { -+ u32 fourcc; -+ enum rkvdec_image_fmt image_fmt; -+}; -+ - struct rkvdec_coded_fmt_desc { - u32 fourcc; - struct v4l2_frmsize_stepwise frmsize; - const struct rkvdec_ctrls *ctrls; - const struct rkvdec_coded_fmt_ops *ops; - unsigned int num_decoded_fmts; -- const u32 *decoded_fmts; -+ const struct rkvdec_decoded_fmt_desc *decoded_fmts; - u32 subsystem_flags; - }; - -@@ -104,6 +114,7 @@ struct rkvdec_ctx { - const struct rkvdec_coded_fmt_desc *coded_fmt_desc; - struct v4l2_ctrl_handler ctrl_hdl; - struct rkvdec_dev *dev; -+ enum rkvdec_image_fmt image_fmt; - void *priv; - }; - --- -2.44.0 - - -From 3fc388dbcec1551a3281048f57e6cf714a83397b Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:09 +0000 -Subject: [PATCH 23/34] media: rkvdec: Add get_image_fmt ops - -Add support for a get_image_fmt() ops that return the required image -format. - -The CAPTURE format is reset when required image format changes and the -buffer queue is not busy. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec.c | 49 +++++++++++++++++++++++++-- - drivers/staging/media/rkvdec/rkvdec.h | 2 ++ - 2 files changed, 49 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 6614a9f777d59..40daf7eb41ead 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -108,15 +108,60 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ struct v4l2_pix_format_mplane *pix_mp = &ctx->decoded_fmt.fmt.pix_mp; -+ enum rkvdec_image_fmt image_fmt; -+ struct vb2_queue *vq; -+ int ret; -+ -+ if (desc->ops->try_ctrl) { -+ ret = desc->ops->try_ctrl(ctx, ctrl); -+ if (ret) -+ return ret; -+ } -+ -+ if (!desc->ops->get_image_fmt) -+ return 0; - -- if (desc->ops->try_ctrl) -- return desc->ops->try_ctrl(ctx, ctrl); -+ image_fmt = desc->ops->get_image_fmt(ctx, ctrl); -+ if (ctx->image_fmt == image_fmt) -+ return 0; -+ -+ if (rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat, image_fmt)) -+ return 0; -+ -+ /* format change not allowed when queue is busy */ -+ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, -+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); -+ if (vb2_is_busy(vq)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -+ const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; -+ struct v4l2_pix_format_mplane *pix_mp = &ctx->decoded_fmt.fmt.pix_mp; -+ enum rkvdec_image_fmt image_fmt; -+ -+ if (!desc->ops->get_image_fmt) -+ return 0; -+ -+ image_fmt = desc->ops->get_image_fmt(ctx, ctrl); -+ if (ctx->image_fmt == image_fmt) -+ return 0; -+ -+ ctx->image_fmt = image_fmt; -+ if (!rkvdec_is_valid_fmt(ctx, pix_mp->pixelformat, ctx->image_fmt)) -+ rkvdec_reset_decoded_fmt(ctx); - - return 0; - } - - static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .try_ctrl = rkvdec_try_ctrl, -+ .s_ctrl = rkvdec_s_ctrl, - }; - - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 6f8cf50c5d99a..e466a2753ccfc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -73,6 +73,8 @@ struct rkvdec_coded_fmt_ops { - struct vb2_v4l2_buffer *dst_buf, - enum vb2_buffer_state result); - int (*try_ctrl)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); -+ enum rkvdec_image_fmt (*get_image_fmt)(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl); - }; - - enum rkvdec_image_fmt { --- -2.44.0 - - -From 3de504bb373b72adc47c7fb9be34c4f443875a4d Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 16:55:10 +0000 -Subject: [PATCH 24/34] media: rkvdec: h264: Support High 10 and 4:2:2 profiles - -Add support and enable decoding of H264 High 10 and 4:2:2 profiles. - -Decoded CAPTURE buffer width is aligned to 64 pixels to accommodate HW -requirement of 10-bit format buffers, fixes decoding of: - -- Hi422FR13_SONY_A -- Hi422FR14_SONY_A -- Hi422FR15_SONY_A -- Hi422FR6_SONY_A -- Hi422FR7_SONY_A -- Hi422FR8_SONY_A -- Hi422FR9_SONY_A -- Hi422FREXT18_SONY_A - -The get_image_fmt() ops is implemented to select an image format -required for the provided SPS control. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec-h264.c | 37 ++++++++++++++++------ - drivers/staging/media/rkvdec/rkvdec.c | 33 +++++++++++++++---- - drivers/staging/media/rkvdec/rkvdec.h | 3 ++ - 3 files changed, 57 insertions(+), 16 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 815d5359ddd5c..baac6d012dddf 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-h264.c -+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -1027,24 +1027,42 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, - return 0; - } - -+static enum rkvdec_image_fmt rkvdec_h264_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_H264_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_8BIT; -+ else -+ return RKVDEC_IMG_FMT_420_8BIT; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_10BIT; -+ else -+ return RKVDEC_IMG_FMT_420_10BIT; -+ } -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ - static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, - const struct v4l2_ctrl_h264_sps *sps) - { - unsigned int width, height; - -- /* -- * TODO: The hardware supports 10-bit and 4:2:2 profiles, -- * but it's currently broken in the driver. -- * Reject them for now, until it's fixed. -- */ -- if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ -+ if (sps->chroma_format_idc > 2) -+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ - return -EINVAL; - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) - /* Luma and chroma bit depth mismatch */ - return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0) -- /* Only 8-bit is supported */ -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ - return -EINVAL; - - width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -@@ -1175,4 +1193,5 @@ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { - .stop = rkvdec_h264_stop, - .run = rkvdec_h264_run, - .try_ctrl = rkvdec_h264_try_ctrl, -+ .get_image_fmt = rkvdec_h264_get_image_fmt, - }; -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 40daf7eb41ead..683e43c699231 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -73,7 +73,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) - { - v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -+ ALIGN(pix_mp->width, 64), pix_mp->height); - pix_mp->plane_fmt[0].sizeimage += 128 * - DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); -@@ -193,7 +193,7 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, - .cfg.min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, -- .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, -+ .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422, - .cfg.menu_skip_mask = - BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), - .cfg.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, -@@ -210,11 +210,23 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const struct rkvdec_decoded_fmt_desc rkvdec_h264_vp9_decoded_fmts[] = { -+static const struct rkvdec_decoded_fmt_desc rkvdec_h264_decoded_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12, - .image_fmt = RKVDEC_IMG_FMT_420_8BIT, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV15, -+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV16, -+ .image_fmt = RKVDEC_IMG_FMT_422_8BIT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV20, -+ .image_fmt = RKVDEC_IMG_FMT_422_10BIT, -+ }, - }; - - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { -@@ -237,6 +249,13 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), - }; - -+static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -+ }, -+}; -+ - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -250,8 +269,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_h264_ctrls, - .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - }, - { -@@ -266,8 +285,8 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_vp9_ctrls, - .ops = &rkvdec_vp9_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -- .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_vp9_decoded_fmts, - } - }; - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index e466a2753ccfc..9a9f4fced7a18 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -80,6 +80,9 @@ struct rkvdec_coded_fmt_ops { - enum rkvdec_image_fmt { - RKVDEC_IMG_FMT_ANY = 0, - RKVDEC_IMG_FMT_420_8BIT, -+ RKVDEC_IMG_FMT_420_10BIT, -+ RKVDEC_IMG_FMT_422_8BIT, -+ RKVDEC_IMG_FMT_422_10BIT, - }; - - struct rkvdec_decoded_fmt_desc { --- -2.44.0 - - -From 19a9b15e6edac171f31f9ca2455a0939eb46bfde Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 23:36:08 +0000 -Subject: [PATCH 25/34] media: rkvdec: Add HEVC backend - -The Rockchip VDEC supports the HEVC codec with the Main and Main10 -Profile up to Level 5.1 High tier: 4096x2304@60 fps. - -Add the backend for HEVC format to the decoder. - -Signed-off-by: Alex Bee <knaerzche@gmail.com> -Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> -Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/TODO | 7 - - .../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec-hevc.c | 814 ++++++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 76 + - drivers/staging/media/rkvdec/rkvdec.h | 1 + - 7 files changed, 2741 insertions(+), 8 deletions(-) - create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c - create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c - -diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile -index cb86b429cfaac..a77122641d141 100644 ---- a/drivers/staging/media/rkvdec/Makefile -+++ b/drivers/staging/media/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO -index 2c0779383276e..f089ef859e8c5 100644 ---- a/drivers/staging/media/rkvdec/TODO -+++ b/drivers/staging/media/rkvdec/TODO -@@ -1,10 +1,3 @@ --* Support for HEVC is planned for this driver. -- -- Given the V4L controls for that CODEC will be part of -- the uABI, it will be required to have the driver in staging. -- -- For this reason, we are keeping this driver in staging for now. -- - * Evaluate introducing a helper to consolidate duplicated - code in rkvdec_request_validate and cedrus_request_validate. - The helper needs to the driver private data associated with -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c -new file mode 100644 -index 0000000000000..eac4ea604949f ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c -@@ -0,0 +1,1848 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder driver -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke <sebastian.fricke@collabora.com> -+ */ -+ -+#include <linux/types.h> -+ -+#define RKV_CABAC_TABLE_SIZE 27456 -+ -+/* -+ * This file is #include from rkvdec-hevc.c and not compiled. -+ */ -+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, -+ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, -+ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, -+ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, -+ 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, -+ 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, -+ 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, -+ 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, -+ 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, -+ 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, -+ 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x47, 0x57, -+ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, 0x47, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, 0x57, 0x5e, -+ 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, 0x4f, -+ 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f, -+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, -+ 0x66, 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, -+ 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, -+ 0x07, 0x57, 0x4f, 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, -+ 0x47, 0x67, 0x40, 0x40, 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, -+ 0x4e, 0x47, 0x47, 0x00, 0x0f, 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, -+ 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, -+ 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66, 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, -+ 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07, -+ 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x45, 0x48, 0x20, -+ 0x57, 0x66, 0x66, 0x56, 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0x0f, 0x0f, 0x17, 0x1f, -+ 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, 0x0f, -+ 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, -+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, -+ 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, -+ 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, -+ 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, -+ 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, -+ 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+}; -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -new file mode 100644 -index 0000000000000..0c4ddc073a6c8 ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,814 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder HEVC backend -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke <sebastian.fricke@collabora.com> -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon <boris.brezillon@collabora.com> -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen <jeffy.chen@rock-chips.com> -+ */ -+ -+#include <media/v4l2-mem2mem.h> -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+#include "rkvdec-hevc-data.c" -+ -+/* Size in u8/u32 units. */ -+#define RKV_SCALING_LIST_SIZE 1360 -+#define RKV_PPS_SIZE (80 / 4) -+#define RKV_PPS_LEN 64 -+#define RKV_RPS_SIZE (32 / 4) -+#define RKV_RPS_LEN 600 -+ -+struct rkvdec_sps_pps_packet { -+ u32 info[RKV_PPS_SIZE]; -+}; -+ -+struct rkvdec_rps_packet { -+ u32 info[RKV_RPS_SIZE]; -+}; -+ -+struct rkvdec_ps_field { -+ u16 offset; -+ u8 len; -+}; -+ -+#define PS_FIELD(_offset, _len) \ -+ ((struct rkvdec_ps_field){ _offset, _len }) -+ -+/* SPS */ -+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) -+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) -+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) -+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) -+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) -+#define BIT_DEPTH_LUMA PS_FIELD(36, 4) -+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) -+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) -+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) -+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) -+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) -+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) -+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) -+#define AMP_ENABLED_FLAG PS_FIELD(66, 1) -+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) -+#define PCM_ENABLED_FLAG PS_FIELD(68, 1) -+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) -+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) -+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) -+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) -+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) -+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) -+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) -+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) -+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) -+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) -+/* PPS */ -+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) -+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) -+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) -+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) -+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) -+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) -+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) -+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) -+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) -+#define INIT_QP_MINUS26 PS_FIELD(163, 7) -+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) -+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) -+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) -+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) -+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) -+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) -+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) -+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) -+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) -+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) -+#define TILES_ENABLED_FLAG PS_FIELD(190, 1) -+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) -+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) -+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) -+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) -+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) -+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) -+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) -+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) -+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) -+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) -+#define NUM_TILE_COLUMNS PS_FIELD(212, 5) -+#define NUM_TILE_ROWS PS_FIELD(217, 5) -+#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8) -+#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8) -+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_hevc_priv_tbl { -+ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; -+ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; -+}; -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+}; -+ -+struct scaling_factor { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserved[4]; /*16Bytes align*/ -+}; -+ -+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) -+{ -+ u8 bit = field.offset % 32, word = field.offset / 32; -+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); -+ u64 val = ((u64)value << bit) & mask; -+ -+ buf[word] &= ~mask; -+ buf[word] |= val; -+ if (bit + field.len > 32) { -+ buf[word + 1] &= ~(mask >> 32); -+ buf[word + 1] |= val >> 32; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; -+ u32 log2_min_cu_qp_delta_size, scaling_distance; -+ dma_addr_t scaling_list_address; -+ int i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 80 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) -+ /* write sps */ -+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); -+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, -+ LOG2_MAX_PIC_ORDER_CNT_LSB); -+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, -+ LOG2_MIN_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), -+ SCALING_LIST_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), -+ AMP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), -+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { -+ WRITE_PPS(1, PCM_ENABLED_FLAG); -+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_CHROMA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), -+ PCM_LOOP_FILTER_DISABLED_FLAG); -+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ } -+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), -+ LONG_TERM_REF_PICS_PRESENT_FLAG); -+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), -+ SPS_TEMPORAL_MVP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), -+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ -+ /* write pps */ -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), -+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), -+ OUTPUT_FLAG_PRESENT_FLAG); -+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), -+ SIGN_DATA_HIDING_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), -+ CABAC_INIT_PRESENT_FLAG); -+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, -+ NUM_REF_IDX_L0_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, -+ NUM_REF_IDX_L1_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), -+ CONSTRAINED_INTRA_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), -+ TRANSFORM_SKIP_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), -+ CU_QP_DELTA_ENABLED_FLAG); -+ -+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ ctb_log2_size_y = min_cb_log2_size_y + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_y = 1 << ctb_log2_size_y; -+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; -+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); -+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); -+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), -+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), -+ WEIGHTED_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), -+ WEIGHTED_BIPRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), -+ TRANSQUANT_BYPASS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), -+ TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), -+ ENTROPY_CODING_SYNC_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), -+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), -+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), -+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), -+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); -+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); -+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), -+ LISTS_MODIFICATION_PRESENT_FLAG); -+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), -+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); -+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ /* Userspace also provide column width and row height for uniform spacing */ -+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) -+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); -+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) -+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); -+ } else { -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ COLUMN_WIDTH(0)); -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ ROW_HEIGHT(0)); -+ } -+ -+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; -+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+} -+ -+/* -+ * Creation of the Reference Picture Set memory blob for the hardware. -+ * The layout looks like this: -+ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference) -+ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references -+ * + 4 bits of the 13th reference) -+ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and -+ * 21 bits for L1 (4 references + first bit of 5) -+ * [3] 32 bits of padding with 0s -+ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11) -+ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references) -+ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32) -+ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12) -+ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s -+ * [7] 32 bits of padding with 0s -+ * -+ * Thus we have to set up padding in between reference 5 of the L1 list. -+ */ -+static void assemble_hw_rps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params; -+ const struct v4l2_hevc_dpb_entry *dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_rps_packet *hw_ps; -+ int i, j; -+ unsigned int lowdelay; -+ -+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -+ -+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1) -+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4) -+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1) -+#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4) -+ -+#define LOWDELAY PS_FIELD(182, 1) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) -+#define NUM_RPS_POC PS_FIELD(202, 4) -+ -+ for (j = 0; j < run->num_slices; j++) { -+ uint st_bit_offset = 0; -+ uint num_l0_refs = 0; -+ uint num_l1_refs = 0; -+ -+ sl_params = &run->slices_params[j]; -+ dpb = decode_params->dpb; -+ -+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; -+ -+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) -+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; -+ -+ lowdelay = 1; -+ } else { -+ lowdelay = 0; -+ } -+ -+ hw_ps = &priv_tbl->rps[j]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ for (i = 0; i < num_l0_refs; i++) { -+ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]]; -+ -+ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L0(i)); -+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ for (i = 0; i < num_l1_refs; i++) { -+ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]]; -+ int is_long_term = -+ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE); -+ -+ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i)); -+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ WRITE_RPS(lowdelay, LOWDELAY); -+ -+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { -+ if (sl_params->short_term_ref_pic_set_size) -+ st_bit_offset = sl_params->short_term_ref_pic_set_size; -+ else if (sps->num_short_term_ref_pic_sets > 1) -+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); -+ } -+ -+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); -+ WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_RPS_BIT_OFFSET); -+ -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, -+ NUM_RPS_POC); -+ } -+} -+ -+/* -+ * Flip one or more matrices along their main diagonal and flatten them -+ * before writing it to the memory. -+ * Convert: -+ * ABCD AEIM -+ * EFGH => BFJN => AEIMBFJNCGKODHLP -+ * IJKL CGKO -+ * MNOP DHLP -+ */ -+static void transpose_and_flatten_matrices(u8 *output, const u8 *input, -+ int matrices, int row_length) -+{ -+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; -+ -+ matrix_size = row_length * row_length; -+ for (i = 0; i < matrices; i++) { -+ row = 0; -+ x_offset = 0; -+ matrix_offset = i * matrix_size; -+ for (j = 0; j < matrix_size; j++) { -+ y_offset = j - (row * row_length); -+ rot_index = y_offset * row_length + x_offset; -+ new_value = *(input + i * matrix_size + j); -+ output[matrix_offset + rot_index] = *(input + i * matrix_size + j); -+ if ((j + 1) % row_length == 0) { -+ row += 1; -+ x_offset += 1; -+ } -+ } -+ } -+} -+ -+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ int offset = 0; -+ -+ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); -+ offset = 6 * 16 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_16x16, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */ -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32, 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+ offset += 128 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), -+ 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+} -+ -+/* -+ * Required layout: -+ * A = scaling_list_dc_coef_16x16 -+ * B = scaling_list_dc_coef_32x32 -+ * 0 = Padding -+ * -+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0 -+ */ -+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ u8 list_32x32[6] = {0}; -+ -+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); -+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; -+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; -+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); -+} -+ -+static void translate_scaling_list(struct scaling_factor *output, -+ const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ assemble_scalingfactor0(output->scalingfactor0, input); -+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); -+ assemble_scalingdc(output->scalingdc, input); -+ memset(output->reserved, 0, 4 * sizeof(u8)); -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u8 *dst; -+ -+ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ dst = tbl->scaling_list; -+ translate_scaling_list((struct scaling_factor *)dst, scaling); -+ -+ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+static struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, the address of current destination -+ * buffer is returned. -+ */ -+ if (!buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return buf; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t refer_addr; -+ u32 rlc_len; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 yuv_virstride = 0; -+ u32 offset; -+ dma_addr_t dst_addr; -+ u32 reg, i; -+ -+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ -+ if (sps->chroma_format_idc == 0) -+ yuv_virstride = y_virstride; -+ else if (sps->chroma_format_idc == 1) -+ yuv_virstride = y_virstride + y_virstride / 2; -+ else if (sps->chroma_format_idc == 2) -+ yuv_virstride = 2 * y_virstride; -+ -+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ -+ /* config rlc base address */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ -+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* config cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ -+ /* config output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ -+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ -+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ /* config ref pic address */ -+ for (i = 0; i < 15; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); -+ reg = (reg >> (i * 4)) & 0xf; -+ } else { -+ reg = 0; -+ } -+ -+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ writel_relaxed(refer_addr | reg, -+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? -+ dpb[i].pic_order_cnt_val : 0); -+ writel_relaxed(reg, -+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ } -+ -+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ -+ /* config hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ -+ /* config hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_RPS_BASE); -+ -+ reg = RKVDEC_AXI_DDR_RDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ -+ reg = RKVDEC_AXI_DDR_WDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_8BIT; -+ else -+ return RKVDEC_IMG_FMT_420_8BIT; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_10BIT; -+ else -+ return RKVDEC_IMG_FMT_420_10BIT; -+ } -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ kfree(hevc_ctx); -+ return -ENOMEM; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl->new_elems; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ assemble_hw_rps(ctx, &run); -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ /* Start decoding! */ -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .get_image_fmt = rkvdec_hevc_get_image_fmt, -+}; -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 15b9bee92016c..83bf790ed9b7d 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -43,6 +43,7 @@ - #define RKVDEC_RLC_MODE BIT(11) - #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) - #define RKVDEC_MODE(x) (((x) & 0x03) << 20) -+#define RKVDEC_MODE_HEVC 0 - #define RKVDEC_MODE_H264 1 - #define RKVDEC_MODE_VP9 2 - #define RKVDEC_RPS_MODE BIT(24) -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 683e43c699231..1be37d31c2a64 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -164,6 +164,67 @@ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .s_ctrl = rkvdec_s_ctrl, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, -+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, -+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, -+ .cfg.dims = { 600 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { -+ .ctrls = rkvdec_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), -+}; -+ -+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV15, -+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -+ }, -+}; -+ - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, -@@ -257,6 +318,21 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = { - }; - - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .frmsize = { -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 9a9f4fced7a18..2f3bda1df5f07 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -138,6 +138,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - - #endif /* RKVDEC_H_ */ --- -2.44.0 - - -From 705ced51abb3c0d37da2bafcc794202b7b2b9046 Mon Sep 17 00:00:00 2001 -From: Alex Bee <knaerzche@gmail.com> -Date: Sun, 5 Nov 2023 23:36:09 +0000 -Subject: [PATCH 26/34] media: rkvdec: Add variants support - -Different versions of the Rockchip VDEC IP exists and one way they can -differ is what decoding formats are supported. - -Add a variant implementation in order to support flagging different -capabilities. - -Signed-off-by: Alex Bee <knaerzche@gmail.com> -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec.c | 21 ++++++++++++++++++++- - drivers/staging/media/rkvdec/rkvdec.h | 10 ++++++++++ - 2 files changed, 30 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 1be37d31c2a64..d9762471a9cde 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -13,6 +13,7 @@ - #include <linux/interrupt.h> - #include <linux/module.h> - #include <linux/of.h> -+#include <linux/of_device.h> - #include <linux/platform_device.h> - #include <linux/pm.h> - #include <linux/pm_runtime.h> -@@ -332,6 +333,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_hevc_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), - .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, - }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -348,6 +350,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -363,6 +366,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_vp9_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), - .decoded_fmts = rkvdec_vp9_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_VP9, - } - }; - -@@ -1174,8 +1178,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_VP9, -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { -- { .compatible = "rockchip,rk3399-vdec" }, -+ { -+ .compatible = "rockchip,rk3399-vdec", -+ .data = &rk3399_rkvdec_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1186,16 +1199,22 @@ static const char * const rkvdec_clk_names[] = { - - static int rkvdec_probe(struct platform_device *pdev) - { -+ const struct rkvdec_variant *variant; - struct rkvdec_dev *rkvdec; - unsigned int i; - int ret, irq; - -+ variant = of_device_get_match_data(&pdev->dev); -+ if (!variant) -+ return -EINVAL; -+ - rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL); - if (!rkvdec) - return -ENOMEM; - - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; -+ rkvdec->capabilities = variant->capabilities; - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 2f3bda1df5f07..14ce26a6c6186 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -22,6 +22,10 @@ - #include <media/videobuf2-core.h> - #include <media/videobuf2-dma-contig.h> - -+#define RKVDEC_CAPABILITY_HEVC BIT(0) -+#define RKVDEC_CAPABILITY_H264 BIT(1) -+#define RKVDEC_CAPABILITY_VP9 BIT(2) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -63,6 +67,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - base.vb.vb2_buf); - } - -+struct rkvdec_variant { -+ unsigned int capabilities; -+}; -+ - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -@@ -98,6 +106,7 @@ struct rkvdec_coded_fmt_desc { - unsigned int num_decoded_fmts; - const struct rkvdec_decoded_fmt_desc *decoded_fmts; - u32 subsystem_flags; -+ unsigned int capability; - }; - - struct rkvdec_dev { -@@ -110,6 +119,7 @@ struct rkvdec_dev { - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -+ unsigned int capabilities; - }; - - struct rkvdec_ctx { --- -2.44.0 - - -From 5239b261c6f2470d53e08ca5302f0847a9a89b8e Mon Sep 17 00:00:00 2001 -From: Alex Bee <knaerzche@gmail.com> -Date: Sun, 5 Nov 2023 23:36:11 +0000 -Subject: [PATCH 27/34] media: rkvdec: Add RK3288 variant - -Add a RK3288 variant, a version of the Rockchip VDEC IP that only -support HEVC decoding. - -Signed-off-by: Alex Bee <knaerzche@gmail.com> -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index d9762471a9cde..ea53625e33344 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1178,6 +1178,10 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3288_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC, -+}; -+ - static const struct rkvdec_variant rk3399_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | -@@ -1185,6 +1189,10 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - }; - - static const struct of_device_id of_rkvdec_match[] = { -+ { -+ .compatible = "rockchip,rk3288-vdec", -+ .data = &rk3288_rkvdec_variant, -+ }, - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, --- -2.44.0 - - -From 0d36421d519fb3bf786ccde4bc5606f4c19d02b1 Mon Sep 17 00:00:00 2001 -From: Alex Bee <knaerzche@gmail.com> -Date: Sun, 5 Nov 2023 23:36:12 +0000 -Subject: [PATCH 28/34] media: rkvdec: Disable QoS for HEVC and VP9 on RK3328 - -The RK3328 VDEC has a HW quirk that require QoS to be disabled when HEVC -or VP9 is decoded, otherwise the decoded picture may become corrupted. - -Add a RK3328 variant with a quirk flag to disable QoS when before -decoding is started. - -Signed-off-by: Alex Bee <knaerzche@gmail.com> -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 9 +++++++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++ - drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 ++++++++++ - drivers/staging/media/rkvdec/rkvdec.c | 12 ++++++++++++ - drivers/staging/media/rkvdec/rkvdec.h | 4 ++++ - 5 files changed, 37 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 0c4ddc073a6c8..d0a1859d54c12 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -788,6 +788,15 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - -+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { -+ u32 reg; -+ -+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= ~BIT(12); -+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ } -+ - /* Start decoding! */ - writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | - RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 83bf790ed9b7d..740bdb4986340 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -218,6 +218,8 @@ - #define RKVDEC_REG_H264_ERR_E 0x134 - #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) - -+#define RKVDEC_REG_QOS_CTRL 0x18C -+ - #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 - #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 - -diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c -index 0e7e16f20eeb0..cadb9d5923089 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-vp9.c -+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c -@@ -824,6 +824,16 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - - writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ -+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { -+ u32 reg; -+ -+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= ~BIT(12); -+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ } -+ - /* Start decoding! */ - writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | - RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index ea53625e33344..41980583527ef 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1182,6 +1182,13 @@ static const struct rkvdec_variant rk3288_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC, - }; - -+static const struct rkvdec_variant rk3328_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_VP9, -+ .quirks = RKVDEC_QUIRK_DISABLE_QOS, -+}; -+ - static const struct rkvdec_variant rk3399_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | -@@ -1193,6 +1200,10 @@ static const struct of_device_id of_rkvdec_match[] = { - .compatible = "rockchip,rk3288-vdec", - .data = &rk3288_rkvdec_variant, - }, -+ { -+ .compatible = "rockchip,rk3328-vdec", -+ .data = &rk3328_rkvdec_variant, -+ }, - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, -@@ -1223,6 +1234,7 @@ static int rkvdec_probe(struct platform_device *pdev) - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; - rkvdec->capabilities = variant->capabilities; -+ rkvdec->quirks = variant->quirks; - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 14ce26a6c6186..1d5d405da56cb 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -26,6 +26,8 @@ - #define RKVDEC_CAPABILITY_H264 BIT(1) - #define RKVDEC_CAPABILITY_VP9 BIT(2) - -+#define RKVDEC_QUIRK_DISABLE_QOS BIT(0) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -69,6 +71,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - - struct rkvdec_variant { - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct rkvdec_coded_fmt_ops { -@@ -120,6 +123,7 @@ struct rkvdec_dev { - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct rkvdec_ctx { --- -2.44.0 - - -From fdf3a2fda65e994dd4e8dbb0d59263862c8a632a Mon Sep 17 00:00:00 2001 -From: Jonas Karlman <jonas@kwiboo.se> -Date: Sun, 5 Nov 2023 23:36:13 +0000 -Subject: [PATCH 29/34] media: dt-bindings: rockchip,vdec: Add RK3288 - compatible - -Add a RK3288 compatible for a version of the Rockchip VDEC IP that only -support HEVC decoding. - -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 08b02ec167557..0f00e9c86737a 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -16,7 +16,9 @@ description: |- - properties: - compatible: - oneOf: -- - const: rockchip,rk3399-vdec -+ - enum: -+ - rockchip,rk3288-vdec -+ - rockchip,rk3399-vdec - - items: - - enum: - - rockchip,rk3228-vdec --- -2.44.0 - - -From 9d0fe0b8773f4244d87de80e9c4477dc522fafde Mon Sep 17 00:00:00 2001 -From: Alex Bee <knaerzche@gmail.com> -Date: Sun, 5 Nov 2023 23:36:14 +0000 -Subject: [PATCH 30/34] ARM: dts: rockchip: Add vdec node for RK3288 - -RK3288 contains a Rockchip VDEC block that only support HEVC -decoding. Add a vdec node for this. - -Signed-off-by: Alex Bee <knaerzche@gmail.com> -Signed-off-by: Jonas Karlman <jonas@kwiboo.se> ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 949bc1829c8fa..dbf2d3b8f13e1 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1296,6 +1296,21 @@ - power-domains = <&power RK3288_PD_VIDEO>; - }; - -+ hevc: video-codec@ff9c0000 { -+ compatible = "rockchip,rk3288-vdec"; -+ reg = <0x0 0xff9c0000 0x0 0x440>; -+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; -+ assigned-clock-rates = <400000000>, <100000000>, -+ <300000000>, <300000000>; -+ iommus = <&hevc_mmu>; -+ power-domains = <&power RK3288_PD_HEVC>; -+ }; -+ - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1303,7 +1318,7 @@ - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3288_PD_HEVC>; - }; - - gpu: gpu@ffa30000 { --- -2.44.0 - - -From 3120028e91bc5b2d76f720ae3f87a0005c5a9e58 Mon Sep 17 00:00:00 2001 +From 5e28380e64ab5d2a2538e77622831a354516a3bb Mon Sep 17 00:00:00 2001 From: Urja Rannikko <urjaman@gmail.com> Date: Tue, 28 Sep 2021 20:23:13 +0300 -Subject: [PATCH 31/34] Revert "clk: divider: Implement and wire up +Subject: [PATCH 14/17] Revert "clk: divider: Implement and wire up .determine_rate by default" This reverts commit 69a00fb3d6970681c15a23595ec54233ce10295c. @@ -5704,7 +1168,7 @@ in my tree to be able to test the rest of 5.15 rc's. 1 file changed, 23 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c -index c1f426b8a5043..3941b4d984f7d 100644 +index c1f426b8a504..3941b4d984f7 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -452,27 +452,6 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, @@ -5755,10 +1219,10 @@ index c1f426b8a5043..3941b4d984f7d 100644 2.44.0 -From f5c6df9aae773f4635f8070658a7c866768ea205 Mon Sep 17 00:00:00 2001 +From cc4f2a12e70c77d7a9b7b8a42d38c513a08c96f6 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel <sebastian.reichel@collabora.com> Date: Tue, 30 Jul 2024 20:05:05 +0200 -Subject: [PATCH 32/34] mfd: rk8xx: Fix shutdown handler +Subject: [PATCH 15/17] mfd: rk8xx: Fix shutdown handler When I converted rk808 to device managed resources I converted the rk808 specific pm_power_off handler to devm_register_sys_off_handler() using @@ -5857,7 +1321,7 @@ Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> 4 files changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c -index 71c2b80a4678d..1583beef714ad 100644 +index 71c2b80a4678..1583beef714a 100644 --- a/drivers/mfd/rk8xx-core.c +++ b/drivers/mfd/rk8xx-core.c @@ -692,10 +692,11 @@ void rk8xx_shutdown(struct device *dev) @@ -5897,7 +1361,7 @@ index 71c2b80a4678d..1583beef714ad 100644 if (ret) return dev_err_probe(dev, ret, diff --git a/drivers/mfd/rk8xx-i2c.c b/drivers/mfd/rk8xx-i2c.c -index 37287b06dab0d..b8c0c368ab8a2 100644 +index 37287b06dab0..b8c0c368ab8a 100644 --- a/drivers/mfd/rk8xx-i2c.c +++ b/drivers/mfd/rk8xx-i2c.c @@ -213,7 +213,7 @@ static int rk8xx_i2c_probe(struct i2c_client *client) @@ -5910,7 +1374,7 @@ index 37287b06dab0d..b8c0c368ab8a2 100644 static void rk8xx_i2c_shutdown(struct i2c_client *client) diff --git a/drivers/mfd/rk8xx-spi.c b/drivers/mfd/rk8xx-spi.c -index 3405fb82ff9fb..20f9428f94bb9 100644 +index 3405fb82ff9f..20f9428f94bb 100644 --- a/drivers/mfd/rk8xx-spi.c +++ b/drivers/mfd/rk8xx-spi.c @@ -94,7 +94,7 @@ static int rk8xx_spi_probe(struct spi_device *spi) @@ -5923,7 +1387,7 @@ index 3405fb82ff9fb..20f9428f94bb9 100644 static const struct of_device_id rk8xx_spi_of_match[] = { diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h -index 69cbea78b430b..be15b84cff9e9 100644 +index 69cbea78b430..be15b84cff9e 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -1349,7 +1349,7 @@ struct rk808 { @@ -5939,10 +1403,10 @@ index 69cbea78b430b..be15b84cff9e9 100644 2.44.0 -From 5fe1a465e16c25c04731db02349291f87f6d74e4 Mon Sep 17 00:00:00 2001 +From 6b6fe76f0826b0ef24e24fc12d1bdd3810dcc253 Mon Sep 17 00:00:00 2001 From: Robin Murphy <robin.murphy@arm.com> Date: Tue, 20 May 2025 18:10:16 +0100 -Subject: [PATCH 33/34] firmware: smccc: Stub out get_conduit() +Subject: [PATCH 16/17] firmware: smccc: Stub out get_conduit() Various callers use arm_smccc_1_1_get_conduit() to guard their arm_smccc_smc() calls - since the latter is already stubbed out to @@ -5955,10 +1419,10 @@ Signed-off-by: Robin Murphy <robin.murphy@arm.com> 1 file changed, 7 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h -index a3863da1510ee..97dc4d47c6642 100644 +index 50b47eba7d01..9a8169194be7 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h -@@ -315,7 +315,14 @@ enum arm_smccc_conduit { +@@ -320,7 +320,14 @@ enum arm_smccc_conduit { * * When SMCCCv1.1 is not present, returns SMCCC_CONDUIT_NONE. */ @@ -5977,10 +1441,10 @@ index a3863da1510ee..97dc4d47c6642 100644 2.44.0 -From 25841d67a844b9705938754b3664c84da5d33681 Mon Sep 17 00:00:00 2001 +From 939a7826d7623c62d7360980baa2de680cc474dd Mon Sep 17 00:00:00 2001 From: Robin Murphy <robin.murphy@arm.com> Date: Tue, 20 May 2025 18:10:17 +0100 -Subject: [PATCH 34/34] pmdomain: rockchip: Relax SMCCC dependency +Subject: [PATCH 17/17] pmdomain: rockchip: Relax SMCCC dependency Most 32-bit Rockchip platforms do not use PSCI, so having to select ARM_PSCI to satisfy a dependency chain to retain working power domain @@ -5993,7 +1457,7 @@ Signed-off-by: Robin Murphy <robin.murphy@arm.com> 1 file changed, 1 deletion(-) diff --git a/drivers/pmdomain/rockchip/Kconfig b/drivers/pmdomain/rockchip/Kconfig -index 218d43186e5b9..ffe5e7b78494f 100644 +index 218d43186e5b..ffe5e7b78494 100644 --- a/drivers/pmdomain/rockchip/Kconfig +++ b/drivers/pmdomain/rockchip/Kconfig @@ -4,7 +4,6 @@ if ARCH_ROCKCHIP || COMPILE_TEST