author | Felix Yan
<felixonmars@archlinux.org> 2022-08-11 09:02:24 UTC |
committer | Felix Yan
<felixonmars@archlinux.org> 2022-08-11 09:02:24 UTC |
parent | c2b5178bd44526e12148a2e1c152d93e78acd5ed |
PKGBUILD | +5 | -2 |
diff --git a/PKGBUILD b/PKGBUILD index d0a9cb5..9511a5a 100644 --- a/PKGBUILD +++ b/PKGBUILD @@ -4,7 +4,7 @@ pkgname=yosys pkgver=0.12 -pkgrel=6 +pkgrel=7 pkgdesc='A framework for RTL synthesis' arch=('x86_64') url='http://www.clifford.at/yosys/' @@ -13,7 +13,10 @@ depends=('abc' 'bash' 'boost-libs' 'tcl' 'libffi' 'python' 'protobuf') makedepends=('boost') checkdepends=('iverilog') optdepends=('graphviz: Schematics display support' - 'xdot: Display netlists') + 'xdot: Display netlists' + 'yices: default solver for yosys-smtbmc' + 'cvc4: alternative solver for yosys-smtbmc' + 'z3: alternative solver for yosys-smtbmc') options=('!lto') # getting SIGSEGV when running the tests with LTO source=("https://github.com/cliffordwolf/yosys/archive/$pkgname-$pkgver.tar.gz") sha512sums=('df91ea75ae08c7c7e134cfa6284c4e9349e6f85f2df32e4710a571176d5e1a334a6e1e77d52bf573686d33b405559e40af1a8d42cbd4e1f95f0e3b4e212e0b06')